Thanks, Amin. I see that. But for writeback operation, see src/mem/cache/cache_implement.hh, function "access()". Regardless of hit/miss, I did not see the latency used for that. Especially for miss, it will allocate a new block directly and writeback
On Thu, Jul 10, 2014 at 11:12 PM, Amin Farmahini <[email protected]> wrote: > Well, grep does not result in any readLatency ... > hitLatency and responseLatency are what you are looking for and they are > used for both reads and writes. See src/mem/cache/base.cc. > > Thanks, > Amin > > > On Thu, Jul 10, 2014 at 8:31 PM, Qi Jia via gem5-users < > [email protected]> wrote: > >> Hi, everyone, >> >> I am looking at codes in classical cache. I find for Read operation, the >> codes consider the readLatency. But for writeback, no latency is >> considered, even if it is a write miss, we still allocate a new block >> directly and write the new data. Then does it mean every writeback would be >> considered as a write hit? >> >> Please correct me if I am wrong. Any suggestion is appreciated, thanks in >> advance. >> >> -- >> Qi Jia >> Graduate Student >> Department of Electrical and Computer Engineering >> North Carolina State University, Raleigh >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > -- Qi Jia Graduate Student Department of Electrical and Computer Engineering North Carolina State University, Raleigh
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