Hello everybody, I'm trying to model on-chip DRAM that acts as the last level cache. The system I want to model has four WideIO controllers for the on-chip DRAM and two DDR3 controllers for the off-chip DRAM.
I tried to add the on-chip memory controllers the same way I would add a shared L3 cache in the CacheConfig.py but no luck so far. Does anybody have any pointers? Thanks, Andreas Prodromou
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