Andreas, Could you give a summary of what kinds of changes would be necessary to fix this issue and how difficult they would be? x86 is not my forte and I've only messed around with the decode/execute part of gem5 once a while back. However, we would be interested in having x86 SMP support with classic memory, so if there's any chance I could wrap my mind around how to do it, I'd be willing to contribute the changes.
Thanks, Paul On Wed, Aug 27, 2014 at 3:48 AM, Andreas Hansson via gem5-users < gem5-users@gem5.org> wrote: > Hi Chao, > > Unfortunately the classic memory system does not support X86 atomic RMW > operations. This is why it works in atomic and not in timing. > > You options are: > 1) implement a fix and do everyone a big favour (I vote for this one) > 2) take the hit in simulation speed and switch to Ruby and stick to timing > mode > 3) use another ISA, e.g. ARM :-), that does not have this problem > > I hope that explains it. > > Andreas > > From: Chao Zhang via gem5-users <gem5-users@gem5.org> > Reply-To: Chao Zhang <zhang.c...@pku.edu.cn>, gem5 users mailing list < > gem5-users@gem5.org> > Date: Wednesday, 27 August 2014 07:47 > To: gem5 users mailing list <gem5-users@gem5.org> > Subject: [gem5-users] How many cpu does the x86 vmlinux SMP kernel > support? > > Dear all, > > I’m currently working on x86 FS on classical memory system to simulate > cache system. But I found the kernel booting just hangs before loading > benchmark script. It does not work when I set 3 or more x86 timing simple > cpus, but it does work when I set them as atomic cores. And it also works > when I set cpu number to 1. The gem5 change set version is 10242, the > kernel is the SMP version from gem5 website (x86_64-vmlinux-2.6.28.4-smp), > and I use default fs.py configuration. > > So I want to know how many x86 timing cores does this SMP kernel > support? Or is this a memory system problem? > > Chao Zhang > Peking University > > > > > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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