Hello everyone,
I tried using the pre fetchers already in Gem5 (mostly stride and tagged) next
to the L2 in the simple cache model (no Ruby) with just L1s and a single L2.
From past emails I figured this should be supported, but I'm getting assertion
failures in regards to the number of contexts the pre fetchers have been set
for. So I just want to make sure firstly how to increase the contexts (I only
see the default initialization of "Max_Contexts" to 64) and if there is any
issues with using pre fetchers in the LLC. This is with gem5-dev and stable.
The assertion:
gem5.opt: build/X86_MESI_Two_Level/mem/cache/prefetch/stride.cc:66: virtual
void StridePrefetcher::calculatePrefetch(Packet*&, std::list<long unsigned
int>&, std::list<Cycles>&): Assertion `master_id < Max_Contexts' failed.
For tagged, it's a little different: gem5.opt:
build/X86_MESI_Two_Level/mem/request.hh:575: int Request::threadId() const:
Assertion `privateFlags.isSet(VALID_THREAD_ID)' failed
Perhaps it has something to do with the thread ID propagating properly to the
prefetcher.
I enable prefetchers by:
system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l2_size,
assoc=options.l2_assoc)
system.l2.prefetch_on_access = 'true'
system.l2.prefetcher = StridePrefetcher(degree=8, latency=1)
(this is for the stride prefetcher case in common/CacheConfig.py).
Thank you!
George M_______________________________________________
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