Hi all, I saw in stats.txt there are information about memory bandwidth for mem_ctrls. But I did not find this kind of information for cache memory. I want to know if there are any information about (or related to) L1/L2 cache bandwidth ?
Thanks -- Cordialement / Best Regards SENNI Sophiane Ph.D. candidate - Microelectronics LIRMM - www.lirmm.fr _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
