Hi, I have a question about a scenario that might result in a deadlock in gem5 (ruby) with X86 and MESI_Two_Level. This is a specific scenario but might be applicable in other cases as well.
Here it goes: Assume: 4-Way L1 cache 1. Locked_RMW_Read (address A) -- L1 cache hit (state: M) 2. Load (address B in same set as A) -- L1 cache hit (state: S) 3. Load (address C in same set as A) -- L1 cache hit (state: S) 4. Load (address D in same set as A) -- L1 cache hit (state: S) 5. Load (address E in same set as A) -- cache miss and triggers L1 replacement on address A (address A state: M_I) 6. Locked_RMW_Write (address A) Request 6 will never complete because address A in TBE will always remain in state M_I. L1 will never accept the message WB_ACK for address A from L2 because it has a block on that address from Mandatory Queue. Is my understanding correct? Can someone enlighten me on this? Thanks, Arpit
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