Hello everybody,
Part of my research project is to run experiments where I constanly switch
from timing to o3 model back and forth (--repeat-switch option). In
particular I am using X86 with both MESI and MOESI.
However, after many switches, I faced some problems while draining the O3
model: I either hit the assert(!memReq) assertion in drainSanityCheck() or
got stuck in the draining process until I reached the maxtick count and the
simulation ended.
After some debugging I could found the causes of the errors and I was able
to switch thousands of times per run. Although it worked fine for my
project, it is probable that these changes mess up other parts of the code.
In this post I want to do two things:
- Ask if anyone can identify a condition where the modifications I did will
result in an error in the simulator
- Make public the changes so other people can use it
In particular, the changes I did are:
/src/cpu/o3/fetch_impl.hh
@@ -738,7 +738,7 @@
decoder[tid]->reset();
// Clear the icache miss if it's outstanding.
- if (fetchStatus[tid] == IcacheWaitResponse) {
+ if (fetchStatus[tid] == IcacheWaitResponse || fetchStatus[tid] ==
IcacheWaitRetry) {
DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
tid);
memReq[tid] = NULL;
/src/cpu/o3/lsq_impl.hh
@@ -175,8 +175,10 @@
}
if (retryTid != InvalidThreadID) {
- DPRINTF(Drain, "Not drained, the LSQ has blocked the caches.\n");
- drained = false;
+ if(thread[retryTid].isLoadBlocked ||
thread[retryTid].isStoreBlocked) {
+ DPRINTF(Drain, "Not drained, the LSQ has blocked the
caches.\n");
+ drained = false;
+ }
}
return drained;
/src/cpu/o3/lsq_unit.hh
@@ -466,12 +466,14 @@
/** The packet that needs to be retried. */
PacketPtr retryPkt;
+ public: //May be there is a better way than make it public, but I need
to know when the store and load are blocked
/** Whehter or not a store is blocked due to the memory system. */
bool isStoreBlocked;
/** Whether or not a load is blocked due to the memory system. */
bool isLoadBlocked;
+ private:
/** Has the blocked load been handled. */
bool loadBlockedHandled;
/src/mem/ruby/system/RubyMemoryControl.cc
@@ -675,7 +675,7 @@
{
DPRINTF(RubyMemory, "MemoryController drain\n");
if(m_event.scheduled()) {
- deschedule(m_event);
+ //deschedule(m_event); //Why does it deschedules? If a store
request is in flight while draining, it won't be satisfied and the cpu
won't drain
}
return 0;
}
If these changes don't generate any other error somewhere else in the code,
do you think I should add it as a patch? If so, what is the process?
Thank you very much
--
Alberto Javier Naranjo-Carmona
M.S. Student Computer Engineering
Texas A&M University, College Station, TX
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