Hi all, I have run the dijkstra benchmark on single-core system successfully. Actually, I was making mistake in passing the arguments to workload (i.e the input data file was not read correctly , so a page table fault was generated). I worked around by changing the source code of dijkstra such that name of input file is not needed to be passed as argument (i.e name of input data file is hard coded in the source code).
However, regarding second part of my question, what I found after searching on net is that there are two version of dijkstra implementation sequential one and parallel one (using pthread.h). Please correct me if I am wrong. I compiled the source code of parallel version and now using the statically created binay as workload for the my script (posted in preiously). However, I get the following error fatal: syscall set_tid_address (#256) unimplemented Can someone please guide me how to remove this error? I know that implementation for this syscall is missing but how can I implement? I have no idea what this function is supposed to do. Any help will be much appreciated. Thanks > > Hi guys, > > I am desperate need of your help. I am trying to solve this problem for > last 2 days but could not solve it. I have two questions. > > 1) I sucessfully ran the "hello world" program on my simulation script > (with one processor), then I change the workload to run a queens benchmark > for 12x12, and it was also sucessfull. However, when I try to run the > dijkstra benchmark using exactly same configuration script, I get the > Page Table fault( as given below.) > > -------------------------------------- > build/ARM/gem5.opt --stats-file=A7Freq1000MHz > configs/MyScripts/Stage0_PN.py --num_cpus=1 --Volts=1mV --Clocks=1000MHz > --I_Cache=32kB --D_Cache=32kB --TLB_Size=512kB > gem5 Simulator System. http://gem5.org > gem5 is copyrighted software; use the --copyright option for details. > > gem5 compiled Oct 1 2014 19:17:30 > gem5 started Oct 20 2014 21:40:03 > gem5 executing on naveed-desktop > command line: build/ARM/gem5.opt --stats-file=A7Freq1000MHz > configs/MyScripts/Stage0_PN.py --num_cpus=1 --Volts=1mV --Clocks=1000MHz > --I_Cache=32kB --D_Cache=32kB --TLB_Size=512kB > Global frequency set at 1000000000000 ticks per second > 0: system.cpu.isa: ISA system set to: 0 0xb892200 > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 > info: Entering event queue @ 0. Starting simulation... > info: Increasing stack size by one page. > Usage: dijkstra <filename> > Only supports matrix size is #define'd. > panic: Page table fault when accessing virtual address 0 > @ tick 20109000 > [invoke:build/ARM/sim/faults.cc, line 70] > Memory Usage: 199012 KBytes > Program aborted at tick 20109000 > Aborted (core dumped) > ------------------------------------------------ > > > My second question is that how can I distribute the workload (e.g single > dijkstra exe) on dual core system? Does the following piece of code > distribute the workload (e.g single dijkstra program execution) on 2/more > processors ? > > root.workload = LiveProcess(cmd= '-o Mibench/input.dat > > Mibench/output_small.dat', executable ='Mibench/dijkstra_small_obj') > > for cpu in mycpu: > cpu.workload=root.workload > > > > I am pasting here the full content of my script file. Thanks you all in > advance. > > ------------------------------------------------ > import optparse > import sys > import m5 > from m5.defines import buildEnv > from m5.objects import * > from m5.util import addToPath, fatal > addToPath('../common') > from FSConfig import * > from SysPaths import * > from Benchmarks import * > import Simulation > import CacheConfig > import MemConfig > from Caches import * > import Options > from O3_ARM_v7a import * > > > parser = optparse.OptionParser() > parser.add_option("--num_cpus", type="int")#adding a new option for script > parser.add_option("--I_Cache",type="string") > parser.add_option("--D_Cache",type="string") > parser.add_option("--TLB_Size",type="string") > parser.add_option("--Volts",type="string") > parser.add_option("--Clocks",type="string") > Options.addCommonOptions(parser) > Options.addFSOptions(parser) > (options, args) = parser.parse_args() > > np = options.num_cpus#reading number of processors input by user > #read Voltage domains > Volts= [] > if options.Volts!= "": > Volts = options.Volts.split(',') > #read clock domains > Clocks=[] > if options.Clocks!= "": > Clocks= options.Clocks.split(',') > #read I Cache sizes > I_Cache=[] > if options.I_Cache!= "": > I_Cache= options.I_Cache.split(',') > #read D Cache sizes > D_Cache=[] > if options.D_Cache!= "": > D_Cache= options.D_Cache.split(',') > #read TLB sizes > TLB_Size=[] > if options.TLB_Size!= "": > TLB_Size= options.TLB_Size.split(',') > > #define voltage domains based on values entered by user > VoltageDomainList= [VoltageDomain(voltage =Volts[i]) for i in xrange(np)] > #define clock domains based on values entered by user > ClockDomainList= > [SrcClockDomain(clock=Clocks[i],voltage_domain=VoltageDomainList[i]) for i > in xrange(np)] > > #define L1 Instruction Cache list > L1ICacheList=[O3_ARM_v7a_ICache(size=I_Cache[i]) for i in xrange(np)] > #define L1 Data Cache list > L1DCacheList=[O3_ARM_v7a_DCache(size=D_Cache[i]) for i in xrange(np)] > > > #define L2 TLB List > ArmTLBList=[O3_ARM_v7aWalkCache(size=TLB_Size[i]) for i in xrange(np)] > > #define np number of cores > mycpu = [O3_ARM_v7a_3(cpu_id=i,clk_domain=ClockDomainList[i]) for i in > xrange(np)] > > i=0; > for cpu in mycpu:# adding caches to each core > > cpu.addTwoLevelCacheHierarchy(L1ICacheList[i],L1DCacheList[i],ArmTLBList[i]) > i=i+1 > #Craete the system with simple memory > mysystem = System( > cpu=mycpu, > cache_line_size = options.cacheline_size, > physmem = SimpleMemory(), > membus = CoherentXBar(), > mem_mode = 'timing' > ) > > #connect slave port of membus with system port > mysystem.system_port=mysystem.membus.slave > #connect master port of membus with port of physical memory > mysystem.physmem.port=mysystem.membus.master > > > # create the interrupt controller > for cpu in mycpu: > cpu.createInterruptController() > cpu.connectAllPorts(mysystem.membus) > > # Create a top-level voltage domain > mysystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) > # Create a source clock for the system and set the clock period > mysystem.clk_domain = SrcClockDomain(clock = > options.sys_clock,voltage_domain = mysystem.voltage_domain) > > > #declare the root > root = Root(full_system=False,system = mysystem) > > #assign the work load to the system > #root.workload = LiveProcess(cmd= 'hello', executable > ='/home/naveed/Desktop/gem5-dev/tests/test-progs/hello/bin/arm/linux/hello') > #root.workload = LiveProcess(cmd= '', executable > ='/home/naveed/Desktop/gem5-dev/queens12_obj') > root.workload = LiveProcess(cmd= '-o Mibench/input.dat > > Mibench/output_small.dat', executable ='Mibench/dijkstra_small_obj') > > for cpu in mycpu: > cpu.workload=root.workload > > > # instantiate configuration > m5.instantiate() > > exit_event = m5.simulate() > print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() > ------------------------------------------------ > > > Naveed Ul Mustafa > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > Naveed Ul Mustafa _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
