Hi Tao,Amin, According to gem5 source, MemAccLat is the time difference between the packet enters in the controller and packet leaves the controller. I presume this added with BusLatency and static backend latency should match with system.l2.ReadReq_avg_miss_latency. However i see a difference of approx 50ns.
As mentioned above if MemAccLat is the time a packet spends in memory controller, then it should include the queuing latency too. In that case the value of avgQLat looks suspicious. Is the avgQlat part of avgMemAccLat? Thanks, Prathap On Tue, Nov 4, 2014 at 3:11 PM, Tao Zhang <tao.zhang.0...@gmail.com> wrote: > From the stats, I'd like to use system.mem_ctrls.avgMemAccLat as the > overall average memory latency. It is 63.816ns, which is very close to 60ns > as you calculated. I guess the extra 3.816ns is due to the refresh penalty. > > -Tao > > On Tue, Nov 4, 2014 at 12:10 PM, Prathap Kolakkampadath < > kvprat...@gmail.com> wrote: > >> Hi Toa, Amin, >> >> >> Thanks for your reply. >> >> To discard interbank interference and queueing delay, i have partitioned >> the banks so that the latency benchmark has exclusive access to a bank. >> Also latency benchmark is a pointer chasing benchmark, which will generate >> a single read request at a time. >> >> >> stats.txt says this: >> >> system.mem_ctrls.avgQLat >> 43816.35 # Average queueing delay per DRAM burst >> system.mem_ctrls.avgBusLat >> 5000.00 # Average bus latency per DRAM burst >> system.mem_ctrls.avgMemAccLat >> 63816.35 # Average memory access latency per DRAM >> burst >> system.mem_ctrls.avgRdQLen >> 2.00 # Average read queue length when enqueuing >> system.mem_ctrls.avgGap >> 136814.25 # Average gap between requests >> system.l2.ReadReq_avg_miss_latency::switch_cpus0.data >> 114767.654811 # average ReadReq miss latency >> >> The average Gap between requests is equal to the L2 latency + DRAM >> Latency for this test. Also avgRdQLen is 2 because cache line size is 64 >> and DRAM interface is x32. >> >> Is the final latency sum of avgQLat + avgBusLat + avgMemAccLat ? >> Also when avgRdQLen is 2, i am not sure what amounts to high queueing >> latency? >> >> Regards, >> Prathap >> >> >> >> On Tue, Nov 4, 2014 at 1:38 PM, Amin Farmahini <amin...@gmail.com> wrote: >> >>> Prathap, >>> >>> You are probably missing DRAM queuing latency (major reason) and other >>> on-chip latencies (such as bus latency) if any. >>> >>> Thanks, >>> Amin >>> >>> On Tue, Nov 4, 2014 at 1:28 PM, Prathap Kolakkampadath via gem5-users < >>> gem5-users@gem5.org> wrote: >>> >>>> Hello Users, >>>> >>>> I am measuring DRAM worst case memory access latency(tRP+tRCD >>>> +tCL+tBURST) using a latency benchmark on arm_detailed(1Ghz) with 1MB >>>> shared L2 cache and LPDDR3 x32 DRAM. >>>> >>>> According to DRAM timing parameters, tRP = '15ns, tRCD = '15ns', tCL = >>>> '15ns', tBURST = '5ns'. Latency measured by the benchmark on cache hit is >>>> 22 ns and on cache miss is 132ns. Which means DRAM memory access latency ~ >>>> 110ns. However according to calculation it should be >>>> tRP+tRCD+tCL+tBurst+static_backend_latency(10ns) = 60ns. >>>> >>>> >>>> The latency what i observe is almost 50ns higher than what it is >>>> supposed to be. Is there anything which I am missing? Do any one know what >>>> else could add to the DRAM memory access latency? >>>> >>>> Thanks, >>>> Prathap >>>> >>>> >>>> _______________________________________________ >>>> gem5-users mailing list >>>> gem5-users@gem5.org >>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>>> >>> >>> >> >
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