Hello All,
I would really appreciate if someone answer my question. I really need to
solve this problem .
Best regards,
Hamid
I am trying to add l3 cache to gem5 cache hierarchy.
I modified the option.py by simply adding:
parser.add_option("--l3cache", action="store_true")
and I modified cacheconfig.py as below (highlighted in red )
def config_cache(options, system):
if options.cpu_type == "arm_detailed":
try:
from O3_ARM_v7a import *
except:
print "arm_detailed is unavailable. Did you compile the O3
model?"
sys.exit(1)
dcache_class, icache_class, l2_cache_class, l3_cache_class = \
O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, O3_ARM_v7aL3
else:
dcache_class, icache_class, l2_cache_class, l3_cache_class = \
L1Cache, L1Cache, L2Cache, L3Cache
# Set the cache line size of the system
system.cache_line_size = options.cacheline_size
if options.l3cache:
system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l3_size,
assoc=options.l3_assoc)
system.tol3bus = CoherentBus(clk_domain = system.cpu_clk_domain,
width = 32)
system.l3.cpu_side = system.tol3bus.master
system.l3.mem_side = system.membus.slave
elif options.l2cache:
# Provide a clock for the L2 and the L1-to-L2 bus here as they
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs, and set the L1-to-L2 bus width to 32
# bytes (256 bits).
system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l2_size,
assoc=options.l2_assoc)
system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
width = 32)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
for i in xrange(options.num_cpus):
if options.caches:
icache = icache_class(size=options.l1i_size,
assoc=options.l1i_assoc)
dcache = dcache_class(size=options.l1d_size,
assoc=options.l1d_assoc)
# When connecting the caches, the clock is also inherited
# from the CPU in question
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(),
PageTableWalkerCache())
else:
system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
if options.l3cache:
system.cpu[i].l2 =
l2_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l2_size,
assoc=options.l2_assoc)
system.cpu[i].tol2bus = CoherentBus(clk_domain =
system.cpu_clk_domain,
width = 32)
system.cpu[i].l2.cpu_side = system.cpu[i].tol2bus.master
system.cpu[i].l2.mem_side = system.tol3bus.slave
system.cpu[i].createInterruptController()
if options.l3cache:
system.cpu[i].connectAllPorts(system.tol3bus, system.membus)
elif options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
else:
system.cpu[i].connectAllPorts(system.membus)
return system
-------------------------------------------
when I am simulating i am getting this error:
Listening for system connection on port 3456
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00
2009
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
warn: CoherentBus system.cpu0.tol2bus has no snooping ports attached!
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
warn: CoherentBus system.cpu1.tol2bus has no snooping ports attached!
0: system.remote_gdb.listener: listening for remote gdb #2 on port 7002
warn: CoherentBus system.cpu2.tol2bus has no snooping ports attached!
0: system.remote_gdb.listener: listening for remote gdb #3 on port 7003
warn: CoherentBus system.cpu3.tol2bus has no snooping ports attached!
gem5.opt: build/ALPHA/base/statistics.hh:1216: Derived&
Stats::Vector2dBase<Derived, Stor>::init(Stats::size_type,
Stats::size_type) [with Derived = Stats::Vector2d, Stor = Stats::StatStor,
Stats::size_type = unsigned int]: Assertion `_x > 0 && _y > 0 && "sizes
must be positive!"' failed.
I attached l2 cache for each core to coherent bus but error says that
CoherentBus system.cpu0.tol2bus has no snooping ports attached!
Am I missing something? I would really appreciate if someone point out my
mistake
Regards,
Hamid
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
