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# Authors: Lisa Hsu

# Configure the M5 cache hierarchy config in one place
#

import m5
from m5.objects import *
from Caches_L3_shared import *

def config_cache(options, system):
    if options.cpu_type == "arm_detailed":
        try:
            from O3_ARM_v7a import *
        except:
            print "arm_detailed is unavailable. Did you compile the O3 model?"
            sys.exit(1)

        dcache_class, icache_class, l2_cache_class = \
            O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2
    else:
        dcache_class, icache_class, l2_cache_class, l3_cache_class = \
            L1Cache, L1Cache, L2Cache, L3Cache

    # Set the cache line size of the system
    system.cache_line_size = options.cacheline_size

        # Provide a clock for the L2 and the L1-to-L2 bus here as they
        # are not connected using addTwoLevelCacheHierarchy. Use the
        # same clock as the CPUs, and set the L1-to-L2 bus width to 32
        # bytes (256 bits).
	#################################################
	#modify on 2014,Nov 10, by cyj
	#shared L3,
	##################################################
    if options.l3cache:
		system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
									size=options.l3_size,
									assoc=options.l3_assoc)
		system.tol3bus = CoherentBus(clk_domain = system.clk_domain
									, width = 16)
		system.l3.cpu_side = system.tol3bus.master
		system.l3.mem_side = system.membus.slave
    if options.l2cache and not(options.l3cache):
		system.l2 = l2_cache_class(clk_domain = system.cpu_clk_domain,size = options.l2_size,assoc = options.l2_assoc)
		system.tol2bus = CoherentBus(clk_domain = system.clk_domain,width = 32)
		system.l2.cpu_side = system.tol2bus.master
		system.l2.mem_side = system.membus.slave

    if options.l2cache and options.l3cache:
		i = 0
		while i< options.num_cpus:	
			l2cache = l2_cache_class( clk_domain = system.cpu_clk_domain,
											size = options.l2_size,
										   assoc = options.l2_assoc)
			l2tol3_bus = CoherentBus(clk_domain = system.clk_domain,width = 32) 
			system.cpu[i].tol2bus = l2tol3_bus
			system.cpu[i].l2 = l2cache
			system.cpu[i].l2.cpu_side = system.cpu[i].tol2bus.master
			system.cpu[i].l2.mem_side = system.tol3bus.slave	
			i += 1
			if i< options.num_cpus :
				system.cpu[i].l2 = l2cache
				system.cpu[i].tol2bus = l2tol3_bus
				system.cpu[i].l2.cpu_side = l2tol3_bus.master
				system.cpu[i].l2.mem_side = system.tol3bus.slave
				i += 1
    i = 0
    for i in xrange(options.num_cpus):
       if options.caches:
            icache = icache_class(size=options.l1i_size,
                                  assoc=options.l1i_assoc)
            dcache = dcache_class(size=options.l1d_size,
                                  assoc=options.l1d_assoc)
	
            # When connecting the caches, the clock is also inherited
            # from the CPU in question
            if buildEnv['TARGET_ISA'] == 'x86':
                  system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
                                                       PageTableWalkerCache(),
                                                      PageTableWalkerCache())
            else:
                system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
       system.cpu[i].createInterruptController()
       if not(options.l2cache) and not(options.l3cache):
			system.cpu[i].connectAllPorts(system.membus)
       if options.l2cache and not(options.l3cache):
			system.cpu[i].connectAllPorts(system.tol2bus,system.membus)
       if options.l2cache and options.l3cache:
		   system.cpu[i].connectAllPorts(system.cpu[i].tol2bus,system.membus)
    return system