Hello Yujie,
Here is the code I wrote for enabling private L2 caches. Unfortunately, I
couldn't find the CacheConfig.py for sharing L2 in an even fashion. But I
did that in the same way.
I hope this help you.
Best regards,
Kumail Ahmed
TU Kaiserslautern,
Germany
On Thu, Nov 13, 2014 at 2:19 AM, Yujie Chen <[email protected]> wrote:
> hello Kumail,
> I modify file CacheConfig.py as you guided . But unfortunately ,
> when I execute the cmd :
> "build/X86/gem5.opt \
> --stats-file=DRAM_state.log \
> configs/example/updated_se.py \
> --mem-type=LPDDR2_S4_1066_x32 \
> --caches \
> --cpu-type=detailed --num-cpus=4 \
> --l1i_size 32kB --l1d_size 32kB \
> --l2cache --l2_size 4MB \
> --l3cache --l3_size 8MB \
> -c cyj_test/bechmarks/hello"
> I had got the warns:
> "warn: add_child('l2'): child 'l2' already has parent
> warn: add_child('tol2bus'): child 'tol2bus' already has parent
> warn: add_child('l2'): child 'l2' already has parent
> warn: add_child('tol2bus'): child 'tol2bus' already has parent"
> *and soon , it exited unexpectedly*. I have no idea about what happened.
> Can you show it more detailed to me, or show your configure file to me.
> the accessory is my configure file. Thanks for your response ^_^.
>
>
> best wishes to you!
>
> --
> YujieChen
> School of Computer Science and Technology
> Cluster and Grid Computing Lab
> Services Computing Technology and System Lab
> Huazhong University of Science and Technology
> Wuhan, 430074, China
> Email:[email protected]
>
> At 2014-11-12 22:36:24, "Kumail Ahmed" <[email protected]> wrote:
>
> Hello Yuije,
>
> In the for-loop for allocating CPUs, you can use the modulus operator to
> apply L2 caches evenly,
>
> you will also need to instantiate L1 private caches in a way that you can
> connect them to the system.tol2bus.
>
> Thank you for your answer :)
>
> Kumail Ahmed
> TU Kasierslautern,
> Germany
>
> On Wed, Nov 12, 2014 at 3:13 PM, Yujie Chen <[email protected]> wrote:
>
>> hello,kumail,
>> you can reference the original configure file of cache, namely
>> config/common/CacheConfigure.py , l2 cache is shared among all cpus in the
>> unmodified cacheconfig.py , and the l1 caches are all private. You can
>> create a "l3 cache" and a "l3 cache bus" based on the BaseCache and
>> CoherentBus，and define the l3 cache's cpu_side and mem_side . You can find
>> the detailed answer on the Internet.
>> by the way , I'm also confused about how to share 2 l2 caches
>> between 4 cores : two cpus share one l2 cache. You said you make it , how
>> do you make it ! I'll appreciate it if you response me! Thanks very much!
>>
>>
>>
>>
>> --
>> YujieChen
>> School of Computer Science and Technology
>> Cluster and Grid Computing Lab
>> Services Computing Technology and System Lab
>> Huazhong University of Science and Technology
>> Wuhan, 430074, China
>> Email:[email protected]
>>
>> At 2014-11-11 21:01:32, "Kumail Ahmed via gem5-users" <
>> [email protected]> wrote:
>>
>> Thank you very much andreas :) I did it!
>>
>> Can you tell me how I can add l3cache in the classical memory model? Do I
>> have to create a new l3cache class can share it on the l2 bus?
>>
>> Thanks again,
>> Kumail Ahmed
>> Masters Student
>> TU Kaiserslautern, Germany
>>
>> On Tue, Nov 11, 2014 at 1:56 PM, Andreas Hansson <[email protected]
>> > wrote:
>>
>>> Hi Kumail,
>>>
>>> The crossbar in gem5 supports address striping, so you can create a
>>> “toL2Bus” that interleaves between two L2 caches. Have a look at
>>> config/common/MemConfig.py for how the interleaving is configured (for the
>>> memory channels). You should be able to do something similar.
>>>
>>> Andreas
>>>
>>> From: Kumail Ahmed via gem5-users <[email protected]>
>>> Reply-To: Kumail Ahmed <[email protected]>, gem5 users mailing list <
>>> [email protected]>
>>> Date: Tuesday, 11 November 2014 10:45
>>> To: "[email protected]" <[email protected]>
>>> Subject: [gem5-users] Sharing L2 cache
>>>
>>> Hello,
>>>
>>> How an I share two L2 caches between 4 CPU cores in GEM5. I guess I
>>> have to change the code in Cacheconfig.py.
>>>
>>> Can someone help me with this?
>>>
>>> Thanks,
>>> Kumail Ahmed
>>>
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>>> recipient, please notify the sender immediately and do not disclose the
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>>> information in any medium. Thank you.
>>>
>>> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
>>> Registered in England & Wales, Company No: 2557590
>>> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
>>> 9NJ, Registered in England & Wales, Company No: 2548782
>>>
>>
>>
>>
>>
>>
>
>
>
# Copyright (c) 2012-2013 ARM Limited
# All rights reserved
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2010 Advanced Micro Devices, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Lisa Hsu
# Configure the M5 cache hierarchy config in one place
#
import m5
from m5.objects import *
from Caches import *
def config_cache(options, system):
if options.cpu_type == "arm_detailed":
try:
from O3_ARM_v7a import *
except:
print "arm_detailed is unavailable. Did you compile the O3 model?"
sys.exit(1)
dcache_class, icache_class, l2_cache_class = \
O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2
else:
dcache_class, icache_class, l2_cache_class = \
L1Cache, L1Cache, L2Cache
# Set the cache line size of the system
system.cache_line_size = options.cacheline_size
if options.l2cache:
# Provide a clock for the L2 and the L1-to-L2 bus here as they
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs, and set the L1-to-L2 bus width to 32
# bytes (256 bits).
system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l2_size,
assoc=options.l2_assoc)
system.tol2bus = CoherentXBar(clk_domain = system.cpu_clk_domain,
width = 32)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
#########################################################################
#system.l2_0 = l2_cache_class(clk_domain=system.cpu_clk_domain,
# size=options.l2_size,
# assoc=options.l2_assoc)
#system.l2_1 = l2_cache_class(clk_domain=system.cpu_clk_domain,
# size=options.l2_size,
# assoc=options.l2_assoc)
#system.tol2bus_0 = CoherentXBar(clk_domain = system.cpu_clk_domain,
# width = 32)
#system.tol2bus_1 = CoherentXBar(clk_domain = system.cpu_clk_domain,
# width = 32)
#system.l2_0.cpu_side = system.tol2bus_0.master
#system.l2_0.mem_side = system.membus.slave
#system.l2_1.cpu_side = system.tol2bus_1.master
#system.l2_1.mem_side = system.membus.slave
######################################################################
for i in xrange(options.num_cpus):
if options.caches:
icache = icache_class(size=options.l1i_size,
assoc=options.l1i_assoc)
dcache = dcache_class(size=options.l1d_size,
assoc=options.l1d_assoc)
#########################################################################
#icache_0 = icache_class(size=options.l1i_size,
# assoc=options.l1i_assoc)
#dcache_0 = dcache_class(size=options.l1d_size,
# assoc=options.l1d_assoc)
#icache_1 = icache_class(size=options.l1i_size,
# assoc=options.l1i_assoc)
#dcache_1 = dcache_class(size=options.l1d_size,
# assoc=options.l1d_assoc)
#######################################################################
# When connecting the caches, the clock is also inherited
# from the CPU in question
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(),
PageTableWalkerCache())
#########################################l################################
#system.cpu[0].addPrivateSplitL1Caches(icache_0, dcache_0,
# PageTableWalkerCache(),
# PageTableWalkerCache())
#system.cpu[1].addPrivateSplitL1Caches(icache_0, dcache_1,
# PageTableWalkerCache(),
# PageTableWalkerCache())
#########################################################################
else:
system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
##########################################################################
#system.cpu[0].addPrivateSplitL1Caches(icache_0, dcache_0)
#system.cpu[1].addPrivateSplitL1Caches(icache_1, dcache_1)
#########################################################################
system.cpu[i].createInterruptController()
#########################################################################
#system.cpu[0].createInterruptController()
#system.cpu[1].createInterruptController()
#######################################################################
if options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
########################################################
#system.cpu[0].connectAllPorts(system.tol2bus_0, system.membus)
#system.cpu[1].connectAllPorts(system.tol2bus_1, system.membus)
#########################################################################
else:
system.cpu[i].connectAllPorts(system.membus)
########################################################################
#system.cpu[0].connectAllPorts(system.membus)
#system.cpu[1].connectAllPorts(system.membus)
#######################################################################
return system
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