Hi Leonardo, The simple and short answer: Modules in gem5 do not align all their events to multiples of their clock (perhaps they should).
The long answer: Note that Tick = 1 ps is not fixed and can be changed. It is merely the default. Once a packet leaves the CPU it goes through a cache has a number of inter-dependencies, queues etc. Even on the other side of the cache you are therefore not guaranteed to only see events on clock edges. Thereafter the packet goes to the crossbar which again is event-driven and based on a few timings that are related to its clock, but the outgoing packets are not guaranteed to be sent on clock edges. In a typical case there would also be some form of clock-domain crossing between the cache and crossbar, and possibly between the crossbar and the memory controller. The final step is the memory controller where packets are received without any guarantee on their alignment to clock edges. I hope that answers your question. If you are still using SimpleDRAM I suggest you update gem5. A lot has been fixed since... Andreas On 24/11/2014 19:34, "Leonardo Ecco via gem5-users" <[email protected]> wrote: >How is the CPU speed implemented in GEM5? > >I'm browsing the source code, but can't seem to find the portion that >actually establishes how many simulation ticks actually constitute a >CPU cycle. > >I'm trying to find this out for the following reason: >- I generated memory access traces with GEM5. Each access in the trace >has a timestamp (which is measured in 1 ps ticks). >- However, when I divide the alleged processor cycle time by the >timestamps in the trace, i'm getting a fraction (instead of an >integer). > >I'll elaborate. I use the following command to invoke gem5: > >./gem5.opt --trace-file=output.txt configs/example/se.py >--cpu-type=detailed --sys-clock=1.1GHz --cpu-clock=1.1GHz --caches -c >a2time01 > >This combined to a small modification in the SimpleDRAM code yielded >the trace below (only showing a couple of lines...): > > 1818: system.physmem: Memory request of 64 bytes for address: READ b80 > 39087: system.physmem: Memory request of 64 bytes for address: READ bc0 > 78174: system.physmem: Memory request of 64 bytes for address: READ c00 > 82846: system.physmem: Memory request of 64 bytes for address: READ 5e40 > 87518: system.physmem: Memory request of 64 bytes for address: READ >87f00 > 92190: system.physmem: Memory request of 64 bytes for address: READ bc0 > 122715: system.physmem: Memory request of 64 bytes for address: READ 5e80 > 128169: system.physmem: Memory request of 64 bytes for address: READ 60c0 > 162711: system.physmem: Memory request of 64 bytes for address: READ 5ec0 > 170892: system.physmem: Memory request of 64 bytes for address: READ >87dc0 >(the number on the left represents the simulation tick). > >My point is: a 1.1GHz frequency means a cycle time of approx. >909.09ps. Given the 1ps simulation tick from GEM5, I was expecting >each processor cycle to contain 909 simulation ticks. > >Although most of the trace timestamps are divisible by 909, there are >counter examples: >92190/909=101.419141914191419141914191419141914191419141914191419141914191 >4191\ >419141914191419141914191419141914191 > >This makes no sense, given that the processor and the system clock are >the same. > > >Although this is not exactly important for my experiments, it is >really bothering me. I need to know this so I can have some peace of >mind :) > > > > >Thanks in advance, > Leonardo Ecco. >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
