Hi Arthur Thanks a lot for your reply.
Your interpretation of LAS is what I require. I want to replay execution starting from the Load. It will be really helpful if you can give me hints on how to replay execution from this load instruction. Thanks On Mon, Dec 1, 2014 at 10:54 PM, Vanchinathan Venkataramani < [email protected]> wrote: > Hi Arthur > > Thanks a lot for your reply. > > Your interpretation of LAS is what I require. > > I want to replay execution starting from the Load. It will be really > helpful if you can give me hints on how to replay execution from this load > instruction. > > Thanks > > > On Mon, Dec 1, 2014 at 10:01 PM, Arthur Perais <[email protected]> > wrote: > >> Okay, the next comments assume that you are talking about a load that >> executed before an older store writing to the same address executed, and >> therefore got the wrong value. If what you call LAS refers to something >> else, disregard that. >> >> From what I gathered, the only replay mechanism currently implemented in >> the o3 CPU is there to deal with partial matches with store-to-load >> forwarding. >> For instance, when a load needs data that is part written by a store, and >> part in the dcache. In that case, the instruction is replayed when the >> store writes to the dcache (the mechanism is actually coarser than that but >> you get the idea). >> >> If you want selective replay for memory order violation (which is okay >> but quite complex in my opinion), you need to implement it yourself. This >> entails : >> - Getting all the instructions you need to replay (through register >> dependencies and memory dependencies). >> - Restore their state (clear the Issued flag, clear the Executed flag, >> and so on). >> - Restore dependencies which is non trivial since wakeDependents in >> inst_queue_impl.hh clears dependencies in dep_graph.hh when waking up >> insts. This means that you need to retain dependencies even after >> instructions have issued. You also need to deal with memory dependencies. >> - How do you replay? From the IQ? if so, then you can't free the IQ entry >> upon issue. If not, then you need a particular buffer to replay >> instructions from. >> >> If you want non-selective replay, this should be easier, although >> dependencies still have to be restored and you have to deal with the >> question of where the instructions are replayed from. >> >> Hope this helps, and if anyone sees a gross mistake in what I said, do >> not hesitate. >> >> Le 01/12/2014 14:47, Vanchinathan Venkataramani via gem5-users a écrit : >> >> Hi Andreas >> >> In ARM O3CPU, when there is a load after store violation, the younger >> instructions are being squashed and re-fetched again. >> >> Is it possible to re-execute these instructions instead of squashing >> all the younger instructions? >> >> Thanks >> >> >> >> _______________________________________________ >> gem5-users mailing >> [email protected]http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> >> >> -- >> Arthur Perais >> INRIA Bretagne Atlantique >> Bâtiment 12E, Bureau E303, Campus de Beaulieu >> 35042 Rennes, France >> >> >
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