Hi, I've run multi-threaded applications in fs/se simulation. But I found that the simulator cannot go over the omp_barrier/pthread_barrier. The tracing results show that the cpus repetitively access the same set of addresses (hitting in cache), and dram controllers receive no requests. This is very like the behavior of spin lock.
I notice such behaviors for both timing and detailed cpu models during fs and se simulations. The atomic cpu model behaves normally. I wonder whether the problem is in the execution of atomic instructions that needed by barrier. Has anyone noticed the same problem? thanks, Zehan
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