Hello Users, Is the maximum number of outstanding DRAM memory requests that can be generated by a core at a time is limited by number of MSHRs in its private cache?
For example, In a 4 core system configuration, each core has a private L1 cache with 6 MSHRs each. The systems Last Level cache has 24 MSHRs, which is shared by all the four cores. If a memory intensive program running core 0 generates many L2 data cache read request misses, then the number of outstanding memory requests it can generate at a time is limited by number of L1 MSHRs or L2 MSHRs? Thanks and Regards, Prathap Kumar Valsan
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