Hello Users,
I am trying to understanding write packets queuing in DRAM controller
model. I am looking at 'addToWriteQueue' function. From my understanding so
far, it merges write requests across burst boundaries. Looking at following
if statement:
if ((addr + size) >= (*w)->addr &&
((*w)->addr + (*w)->size - addr) <= burstSize) {
// the new one is just before or partially
// overlapping with the existing one, and together
// they fit within a burst
....
....
....
}
Merging here may make the write request go across burst boundary. Size
computation in the beginning of the for loop of this function suggests that
packets are split at burst boundaries. For example, if the packet addr is
16, burst size is 32 bytes and packet request size is 25 bytes (all in
decimal for ease), then 2 write bursts should be added to the queue: 16-31,
32-40. However, while merging, lets say if there existed a packet already
in write queue from 32-40, then a write from 16-40 is added to the queue
which is across burst boundary. is that physically possible? Shouldn't
there be two write requests in the queue:16-31, 32-40 instead of one single
merged request?
Thank you,
-Rizwana
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