I see. That makes things much clear to me. Thank you, -Rizwana
On Tue, Jan 27, 2015 at 5:44 AM, Andreas Hansson <[email protected]> wrote: > Hi Rizwana, > > It is not the job of the memory controller to implement any specific > memory consistency model. The interconnect and memory controller could give > stronger guarantees to help the cores out, but they don’t have to. In > general the memory-system components in gem5 give no guarantee on the > response order. > > Andreas > > From: Rizwana Begum <[email protected]> > Date: Monday, 26 January 2015 20:45 > To: Andreas Hansson <[email protected]> > Cc: gem5 users mailing list <[email protected]> > Subject: Re: [gem5-users] WAR dependency > > Hello Andreas, > > Thanks for your prompt reply. I am guessing these cases are handled in > lsq_unit in O3CPU. > > I understand the case where read arrives while write to the same address > is pending. Read looks up in the write queue and it is not issued to DRAM > if its found in write queue (both timing and data makes sense to me). > However, its the write arriving after read that's confusing me. Shouldn't > the write be scheduled only after the read pending to that address is > served? Or is it that all requests to MC are independent and therefore read > and write order need not be preserved? Meaning, a write request to a given > address can be issued before a read to the same address is handled? > > Thank you, > -Rizwana > > On Mon, Jan 26, 2015 at 11:37 AM, Andreas Hansson <[email protected] > > wrote: > >> Hi Rizwana, >> >> It is handled in the CPU cores. >> >> Andreas >> >> From: Rizwana Begum via gem5-users <[email protected]> >> Reply-To: Rizwana Begum <[email protected]>, gem5 users mailing list >> <[email protected]> >> Date: Monday, 26 January 2015 16:34 >> To: gem5 users mailing list <[email protected]> >> Subject: [gem5-users] WAR dependency >> >> Hello Users, >> >> I have a basic read-after-write and write-after-read dependency >> question. If DRAM controller receives a write request, then it is added to >> the write queue and its response is sent immediately. When its response is >> being sent, access(pkt) method from AbstractMemory is called which actually >> writes the data. If a read request to the same address was pending in the >> readQueue (note that this read request arrived at DRAM controller before >> the write), then this request would read new data written. Wouldn't this >> violate WAR dependency? (I am sure WAR is handled properly, otherwise >> benchmarks would have resulted in incorrect output, but I don't seem to be >> able to figure out where the dependencies are handled in memory system). >> >> Thank you, >> -Rizwana >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >> confidential and may also be privileged. If you are not the intended >> recipient, please notify the sender immediately and do not disclose the >> contents to any other person, use it for any purpose, or store or copy the >> information in any medium. Thank you. >> >> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, >> Registered in England & Wales, Company No: 2557590 >> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, >> Registered in England & Wales, Company No: 2548782 >> > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 >
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