Hi Andreas This is a late "thanks" for your correct response. :)
Azadeh On Mon, Feb 2, 2015 at 10:43 AM, Andreas Hansson <[email protected]> wrote: > Hi Azadeh, > > I suspect what you read as “data” is later used as an address. > > Andreas > > From: Azadeh Shirvanian <[email protected]> > Date: Saturday, 31 January 2015 19:43 > To: Andreas Hansson <[email protected]>, "[email protected]" < > [email protected]> > Subject: Re: [gem5-users] Error: Tried to read unmapped address > > Hi Andreas > > Thanks for your response. That is weird. So you mean I have flipped the > bits of the address too. But I thought I was modifying the data on data > cache, which only contains data and no address. So I infer that *writeMem > *also involves the instruction cache and not only the data cache. Is that > right? > > Azadeh > > On Wed, Jan 28, 2015 at 7:43 PM, Andreas Hansson <[email protected]> > wrote: > >> Hi Azadeh, >> >> I am not sure what you expected to happen. The “address” you see is >> probably written to memory earlier (as data) and now comes back to you as >> complete gibberish. >> >> Solution: Do not flip bits :-) >> >> Andreas >> >> From: Azadeh Shirvanian via gem5-users <[email protected]> >> Reply-To: Azadeh Shirvanian <[email protected]>, gem5 users >> mailing list <[email protected]> >> Date: Wednesday, 28 January 2015 18:32 >> To: "[email protected]" <[email protected]> >> Subject: [gem5-users] Error: Tried to read unmapped address >> >> Dear all >> >> I am trying to flip every bit of the data, in *writeMem*, the function >> in *src/cpu/simple/timing.cc*, so that the data is faulty before it is >> written to the cache. >> >> I am working on X86, classical memory and running in SE mode. I also >> trace the data and the address exchanged between CPU and L1 data cache >> using CommMonitor. That is the reason why I am working on *timing.cc*. >> >> What I have done: >> >> *1.* I declared in * timing.hh* - right after the declaration of >> *writeMem*: >> >> void faultInject(uint8_t *data, unsigned size); >> >> *2. *Then I defined the function in *timing.cc* to flip every bit of >> the data: >> >> void >> TimingSimpleCPU::faultInject(uint8_t *data, unsigned size) >> { unsigned i,j; >> if (data != NULL) >> for (i=0; i<size; i++) >> for (j=0; j<8; j++) >> data[i] = data[i] ^ (1<<j); >> } >> >> *3. *I called this function inside *writeMem*, as you can see in green: >> >> Fault >> TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, >> Addr addr, unsigned flags, uint64_t *res) >> { >> uint8_t *newData = new uint8_t[size]; >> const int asid = 0; >> const ThreadID tid = 0; >> const Addr pc = thread->instAddr(); >> unsigned block_size = cacheLineSize(); >> BaseTLB::Mode mode = BaseTLB::Write; >> >> if (data == NULL) { >> assert(flags & Request::CACHE_BLOCK_ZERO); >> // This must be a cache block cleaning request >> memset(newData, 0, size); >> } else { >> faultInject(data, size); >> memcpy(newData, data, size); >> } >> >> After compiling: >> scons build/X86/gem5.opt >> >> and running: >> build/X86/gem5.opt configs/example/se.py --cpu-type=timing --caches -c >> tests/test-progs/hello/bin/x86/linux/hello > log.txt >> >> I get the following error: >> >> 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 >> panic: Tried to read unmapped address 0xffff8000000011bf. >> @ tick 630000 >> [invoke:build/X86/arch/x86/faults.cc, line 160] >> Memory Usage: 631820 KBytes >> Program aborted at tick 630000 >> Aborted (core dumped) >> >> Reading email threads and changing my code did not eventually help. >> Thus, I would be really grateful if anyone could clarify the reason of this >> problem and the solution to it. >> >> Azadeh >> >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >> confidential and may also be privileged. If you are not the intended >> recipient, please notify the sender immediately and do not disclose the >> contents to any other person, use it for any purpose, or store or copy the >> information in any medium. Thank you. >> >> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, >> Registered in England & Wales, Company No: 2557590 >> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, >> Registered in England & Wales, Company No: 2548782 >> > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 >
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