Sorry about the mistake made in previous letter.

 hi, all.

 I found there are some switchs like switch cases (C/C++) in the files 
 "decode.cc" or "arm.isa"

 here's the code below:

 -----------------------------------------------------------------

 StaticInstPtr ArmISA::Decoder::decodeInst(ArmISA::ExtMachInst machInst){

 using namespace ArmISAInst; 
     switch (THUMB) { 
         case 0x0:
     switch (AARCH64) { 
         case 0x0:
     switch (COND_CODE) {
         case 0xf:
             // ArmUnconditional::armUnconditional(([], {})) {
                 ...
                 break;
         default: switch (ENCODING) {
             case 0x0:
                 switch (SEVEN_AND_FOUR) {
                 ...
                 ...
                 ...

 -----------------------------------------------------------------

 I'd like know what's the switch criterion?

 Such as "THUMB" , "AARCH64" , "COND_CODE" , "ENCODING" , "SEVEN_AND_FOUR" 
 ...etc.

 Are they defined in the file "arch/arm/types.hh" ? But it seem to be   
different?
 
 here's the code below:

 -----------------------------------------------------------------

 BitUnion64(ExtMachInst)
     // ITSTATE bits
     Bitfield<55, 48> itstate;
     Bitfield<55, 52> itstateCond;
     Bitfield<51, 48> itstateMask;

     // FPSCR fields
     Bitfield<41, 40> fpscrStride;
     Bitfield<39, 37> fpscrLen;

     // Bitfields to select mode.
     Bitfield<36>     thumb;    // here it's what I mentioned
     Bitfield<35>     bigThumb; // here it's what I mentioned
     Bitfield<34>     aarch64;  // here it's what I mentioned

     // Made up bitfields that make life easier.
     Bitfield<33>     sevenAndFour; // here it's what I mentioned
     Bitfield<32>     isMisc;       // here it's what I mentioned
     uint32_t         instBits;

     // All the different types of opcode fields.
     Bitfield<27, 25> encoding;
     ...
     ...
     ...

 -----------------------------------------------------------------
 And in the file "arm.isa" there's a paragraph

 '''
 // The actual ARM ISA decoder
 // --------------------------
 // The following instructions are specified in the ARM ISA
 // Specification. Decoding closely follows the style specified
 // in the ARM ISA specification document starting with Table B.1 or 3-1
 '''

 What's Table B.1 or 3-1? Where's it?
 I've read "ARM Architecture Reference Manual", but I did not find it.

 Thanks!

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