Hello, If you're not doing so already, I'd recommend to start with a known working configuration and incrementally change it toward your desired system. Then it'd be easier to report what piece of configuration is not working.
Hope it helps, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2015-03-20 18:23 GMT+01:00 Naveed Ul Mustafa <[email protected]> : > Hi Andreas and All, > > I am trying to model a system consisting of two MinorCPUs and running > HelloWorld program on both of them but I receive the following error. > > =============================================== > gem5 Simulator System. http://gem5.org > gem5 is copyrighted software; use the --copyright option for details. > > gem5 compiled Oct 1 2014 19:17:30 > gem5 started Mar 20 2015 19:17:48 > gem5 executing on naveed-desktop > command line: build/ARM/gem5.opt configs/MyScripts/mySystem.py > Global frequency set at 1000000000000 ticks per second > 0: system.cpu.isa: ISA system set to: 0 0xc612200 > Segmentation fault (core dumped) > ============================================ > On the other hand, I dont receive the error if my systme consists of onle > one MinorCPU (and mot two). > > I am pasting my .py script here. Please help me to figure out the problem. > > ============================================ > #import m5 > #from m5.objects import * > > import optparse > import sys > import m5 > from m5.defines import buildEnv > from m5.objects import * > from m5.util import addToPath, fatal > addToPath('../common') > from FSConfig import * > from SysPaths import * > from Benchmarks import * > import Simulation > import CacheConfig > import MemConfig > from Caches import * > import Options > > > parser = optparse.OptionParser() > Options.addCommonOptions(parser) > Options.addFSOptions(parser) > (options, args) = parser.parse_args() > > if args: > print "Error: script doesn't take any positional arguments" > sys.exit(1) > CPU1=MinorCPU()#CPU1 is an out of order execution processor > CPU2=MinorCPU()#CPU2 is in-order execution processor with fixed pipeline > > > MyCache=BaseCache(assoc=2, mshrs = 10, tgts_per_mshr=5, hit_latency=1, > response_latency=2)#defining a cache > > MyL1Cache=MyCache(is_top_level= True) > > CPU1.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),#Instruction > Cache, Level1 > MyL1Cache(size = '256kB'),#Data Cache, > Level 1 > MyCache(size = '2MB', hit_latency=2, > response_latency=4)#Level2 Cache > ) > > CPU2.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),#Instruction > Cache, Level1 > MyL1Cache(size = '256kB'),#Data Cache, > Level 1 > MyCache(size = '2MB', hit_latency=2, > response_latency=4)#Level2 Cache > ) > > > > mysystem = System( > cpu=[CPU2], > > physmem = SimpleMemory(), > cache_line_size = options.cacheline_size,#user defined cache line > size > membus = CoherentXBar(), > > mem_mode = 'timing' > ) > mysystem.system_port=mysystem.membus.slave > mysystem.physmem.port=mysystem.membus.master > > CPU1.createInterruptController() > CPU1.connectAllPorts(mysystem.membus) > > CPU2.createInterruptController() > CPU2.connectAllPorts(mysystem.membus) > > > # Create a top-level voltage domain > mysystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) > # Create a source clock for the system and set the clock period > mysystem.clk_domain = SrcClockDomain(clock = > options.sys_clock,voltage_domain = mysystem.voltage_domain) > > > root = Root(full_system=False,system = mysystem) > root.workload=LiveProcess(cmd= 'hello', executable > > ='/home/naveed/Desktop/gem5-dev/tests/test-progs/hello/bin/arm/linux/hello') > > CPU1.workload=root.workload > CPU2.workload=root.workload > > m5.instantiate() > > exit_event = m5.simulate() > > print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() > > > ============================================ > > Thanks a lot guys, looking forward to your guidance. > > > Hi Naveed, > > > > I think there is some confusion here between hardware threads and > > software > > threads. > > > > The MinorCPU, at the moment, does not support hardware multi-threading. > > It > > has no issues running multi-threaded software. > > > > I hope that addresses your concern. > > > > Andreas > > > > On 20/03/2015 16:43, "Naveed Ul Mustafa" <[email protected]> > > wrote: > > > >> > >>Hi Guys, > >> > >>I need your guidance about the following. > >> > >>I am trying to model a system consisting of an in order cpu (I am > >> thinkin > >>to use MinorCPU) and O3 CPU and distribute the workload (for example a > >>benchmark from PARMIBENCH suite) among two CPUs. > >> > >>In documentation, it says that multithreading is not supported for Minor > >>CPU. If so, how can I distribute the workload? > >> > >>Thanks for all your help > >> > >>Naveed Ul Mustafa > >> > >>_______________________________________________ > >>gem5-users mailing list > >>[email protected] > >>http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > > confidential and may also be privileged. If you are not the intended > > recipient, please notify the sender immediately and do not disclose the > > contents to any other person, use it for any purpose, or store or copy > the > > information in any medium. Thank you. > > > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > > Registered in England & Wales, Company No: 2557590 > > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > > Registered in England & Wales, Company No: 2548782 > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > Naveed Ul Mustafa > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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