Hi all, I know, as stated here: http://www.m5sim.org/O3CPU, the gem5 code, at least originally, was modeled loosely after the Alpha 21264.
In the Alpha 21264 paper it makes mention of the out-of-order issue queues that maintain the pending instructions, issuing them as the data becomes ready on the scoreboard. There's specifically this sentence on when it is freed: "The queue is collapsing - an entry becomes immediately available once the instruction issues or is squashed due to miss-speculation." As far as I can tell, the 'out-of-order issue queue' is represented within gem5 as the instruction queue. The IQ is inserted during the IEWs Tick() during the IEWs dispatchInsts(tid) function where it does an insert() into the IQ. This makes sense to me, and loosely follows the paper. The question I have is why the instructionQueue itself doesn't free these entries until the instruction is actually committed? This occurs during the IEWs Tick() in the IEW dispatchInsts(tid) function where it does a instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum, tid). At this point all entries in the instruction queue older then the doneSeqNum are freed within the IQ. This code is in o3/iew_impl.hh:1454. This makes it seem like the IQ entry is persisting for the entire duration of dispatch through commit. Am I missing something here? This clearly is not the intent of the paper, nor do I follow why this would be architecturally correct. My understanding is once the instruction resides within the ROB there shouldn't be any requirement it also remain in the IQ. Additionally, wouldn't this result in a massive waste of IQ entries? I am working on some resource (SMT) style work, and resource allocation/free (and when they occur) are important for that work, but I would also argue in general. Any clarification on this would be great. I very well could be missing something/reasoning (there is a lot of code (: ) Thanks for your time. Kindly, Sam _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
