If you are executing your code in SE mode, such a configuration can be created with adding new CoherentXbar in the se.py file.
You can than connect new caches to these bars through your own logic. PS: I think in future, there should be a graphical tool for making a CPU tool in GEM5. On 10 Apr 2015 12:51 am, "Davesh Shingari" <[email protected]> wrote: > Hi > > Is there a way to simulate following configuration: > > P0 and P1 processors having private L1, shared L2. > P2 having private L1 and L2. > P0, P1, P2 sharing the DRAM. > > Any guidance or link regarding the same will be highly appreciated. > > -- > Have a great day! > > Thanks and Warm Regards > Davesh Shingari > Master's in Computer Engineering [EE] > Arizona State University > > [email protected] > ᐧ > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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