Hi Davesh, With ARM you should use the classic memory system (in some configuration), and thus a MOESI protocol. There is no need to use Ruby.
The cache and crossbar models in the classic memory system provide a very flexible set of components that you can use to build a wide range of on-chip memory systems. Andreas From: Davesh Shingari <[email protected]<mailto:[email protected]>> Reply-To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Wednesday, 15 April 2015 23:45 To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Subject: [gem5-users] ARM - Cache Coherence Protocol Hi In the ARM FS simulation which cache coherence model is used. When I look at the build_opts/ARM, then I can see Protocol as MI_example. If that is the one used then how come 2 level cache hierarchy is implemented (because the MI example has 1 level cache hierarchy)? And ARM uses Classic Memory Model instead of Ruby. If yes, then doesn't it then implements MOESI protocol. if no, then is Ruby supported? -- Have a great day! Thanks and Warm Regards Davesh Shingari Master's in Computer Engineering [EE] Arizona State University [email protected]<mailto:[email protected]> [https://mailfoogae.appspot.com/t?sender=ac2hpbmdhcmlkYXZlc2hAZ21haWwuY29t&type=zerocontent&guid=bde27132-b42f-4480-ace7-bef4c56120df]ᐧ -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
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