Hello all, I am quite lost with the configuration of memory system. I am trying make an architecture as can be seen in the image below [1]
[1] http://postimg.org/image/i4ygm554d/ Where "memoria principal" would be main memory, as a DDR3 or whatever and where scratchpad memory is a instance of SimpleMemory with latencies modified. My question is, is it possible to make the connections as I have shown? And second, can I divide the address space in two parts: for main memory (and cache) and for scratchpad memory? Thanks, -- Marcos Horro Varela University of A Coruña (Galicia, Spain) +34 618 62 67 37 _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
