Hi Prathap,

The most sensible place to implement the arbitration is indeed in the crossbar 
which is conceptually part of the L2 cache. By default the crossbar uses 
First-Come First-Served, but you can change with not too much coding. The 
tricky bit in this case is to base the selection on MSHRs, since the crossbar 
has no such accounting. I would think the easiest is to add outstanding 
transaction counting per SlavePort in the crossbar, and then only let a port 
have X outstanding transactions. Overall this would be valuable functionality, 
so if you do code it up, please post a patch. It would be a great contribution.

Andreas

From: Prathap Kolakkampadath <[email protected]<mailto:[email protected]>>
Reply-To: gem5 users mailing list 
<[email protected]<mailto:[email protected]>>
Date: Monday, 4 May 2015 20:18
To: gem5 users mailing list <[email protected]<mailto:[email protected]>>
Subject: [gem5-users] Query regarding blocking cache slave port

Hello All,

I am simulating an ARM O3 multi-core system with private L1 cache and a Shared 
L2 cache.
I am investigating the MSHR contention in the L2 cache. If cache has no free 
MSHRs, this Marks the access path of the cache as blocked and also sets the 
blocked flag in the slave interface.This means there won't be any further 
access to the L2 cache.
Instead of blocking the L2 cache altogether, i would like to place a MSHR 
reservation to a selected core. So that requests from only selected core are 
blocked based on its respective MSHR utilization.

I am not sure if this is feasible. Do L2 Bus has an arbitrator which can be 
modified to do this?

Thanks,
Prathap

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