Hello, To my understanding, width of pipeline stages is in uops.
Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2015-05-25 2:06 GMT+02:00 Ayaz Akram <[email protected]>: > I have a very basic question, Is width defined in terms of No. of > Instructions always? For instance let's say I want to simulate an x86 > pipeline with issue width of 8 simple uops/cycle. Should I set issue width > as 8 or 4 (fused uops/instructions ) ? > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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