Hi Prathap, We have some patches to restrict way allocation in the cache itself (not per core though). You can probably use that as a starting point. I’m afraid beyond that you will need to add the appropriate functionality to look at e.g. masterId and decide on a way. I’ll try and get those patches posted in the next few days.
Andreas From: Prathap Kolakkampadath <[email protected]<mailto:[email protected]>> Reply-To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Monday, 8 June 2015 17:29 To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Subject: [gem5-users] L2 cache partitioning Dear Users, I am using ARM Full System configuration, where L2 is 8-way set associative shared Last Level Cache. I am trying to partition the L2 cache by ways among four cores, so that each core gets two ways. Is there a hardware support(configuration register) available to do this? If not can anyone throw some pointers to achieve way partitioning. Thanks in advance. Prathap -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
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