Hello, I am trying to use DVFS for my project. But I want the frequency control in hardware so I cannot use the DVFS support given by Gem5 as that is on kernel level. For my project I added each core and their l1 caches to a different clock domains and hacked the code to change the frequency of the domains whenever I wanted.
To check if it is working I fired two runs, one with default frequency settings (which is 2 Ghz) and in the other run I double the frequency of each domain, so each core runs on 4Ghz. Now looking at the stats, I see simulation time dropping to almost half which is expected. But I am not able to reason the cache stats. I am seeing the cache misses for all caches also decreasing by almost half. Can anybody reason how is that happening? I am running arm Full system with classic memory model. All memory settings are default. Thanks, -- Warm regards Nimish Girdhar Department of Electrical and Computer Engineering Texas A&M University
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