Hi Andreas,
Thank you for your sincere help. I've tried again, and it is OK to connect two caches back to back. I want to model a new cache with several sub-modules and each of them may contribute to latency. So I'm wondering that in which means I could connect two memory objects. Does the way of using ports and packet best fits into my situation? I'm new to gem5 and many thanks. Best regrads, Will At 2015-07-16 22:59:14, "Andreas Hansson" <[email protected]> wrote: Hi Will, In general you should be fine to connect two caches back to back. The question is, why would you? Why not make one of the caches larger? Andreas From: gem5-users <[email protected]> on behalf of Will <[email protected]> Reply-To: gem5 users mailing list <[email protected]> Date: Thursday, 16 July 2015 15:56 To: m5-users <[email protected]> Subject: [gem5-users] Could cache connected without bus? Hello, I'v attempted to connect two caches without bus but I got error. Does anybody knows whether I could connect two memory objects directly, i.e without bus? I would appreciate if some one can shed some light on this. Best regards, Will -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
