Payne, Benjamin <bpayne <at> lps.umd.edu> writes: > > > I am also interested in using RAM simulators with gem5. On the gem5 wiki I read > http://gem5.org/Ruby > What is the difference between using the built-in Ruby memory simulation and DRAMSim2? > > It looks like there are lots of tuning options based on > http://gem5.org/Coherence-Protocol-Independent_Memory_Components > http://gem5.org/Cache_Coherence_Protocols > > > From: gem5-users-bounces <at> gem5.org [mailto:gem5-users-bounces <at> gem5.org] On Behalf Of Rizwana BegumSent: Tuesday, November 13, 2012 10:16 AMTo: gem5 users mailing listSubject: Re: [gem5-users] DRAMSim2 patch integration with Gem5 for 'fs' mode > > Thank you Andreas for your reply. > > I have tried conf_table_reported already and that didn't work, it throws similar errors. > > I am giving a try to simpleDRAM. I was just wondering if I could know what timing models it is using and the details of its memory model. Does gem5 has any documentation on simleDRAM? > > Thank you > > -Rizwana > > On Fri, Nov 9, 2012 at 9:33 AM, Andreas Hansson <Andreas.Hansson <at> arm.com> wrote: > Hi Rizwana,Add the conf_table_reported = True to the memories you want the OS to see.You might also want to give the built-in DRAM controller model a go. With the default settings it models a simple DDR3 controller.AndreasFrom: Rizwana Begum <rizwana.043 <at> gmail.com<mailto:rizwana.043 <at> gmail.com>>Reply-To: gem5 users mailing list <gem5-users <at> gem5.org<mailto:gem5-users <at> gem5.org>>Date: Friday, 9 November 2012 14:26To: "gem5-users <at> gem5.org<mailto:gem5-users <at> gem5.org>" <gem5-users <at> gem5.org<mailto:gem5-users <at> gem5.org>>Subject: [gem5-users] DRAMSim2 patch integration with Gem5 for 'fs' mode > Hello All,I am trying to integrate the dramsim2 patch released recently by Tao Zhang located <at> http://www.mail-archive.com/gem5- users <at> gem5.org/msg05088.html (also attached) with gem5 for 'fs' mode (patch is integrated and tested for 'se' mode). I made changes in FSConfig.py file to set the 'physmem' to DRAMSim2 memory. Following is the change that I had to make to integrate DRAMSim2.- ======================================================================== ============== # self.physmem = SimpleMemory(range = # AddrRange(self.realview.mem_start_addr, # size = mdesc.mem()), # conf_table_reported = True) self.physmem = DRAMSim2( range = AddrRange(self.realview.mem_start_addr,size=mdesc.mem()), cpu_clock="2GHz", deviceConfigFile = os.path.join("/home/DREXEL/rb639/PowerAgileComputing/gem5/ext/DRAMSim2/i ni/DDR3_micron_16M_8B_x8_sg15.ini"), systemConfigFile=os.path.join("/home/DREXEL/rb639/PowerAgileComputing/ge m5/ext/DRAMSim2/system.ini.example"), )- ======================================================================== ==============Once I make this change, following is the error log:- ======================================================================== ==============warn: This is an integrated DRAMsim v2 moduleListening for system connection on port 5900Listening for system connection on port 34560: system.remote_gdb.listener: listening for remote gdb #0 on port 7000fatal: Expected a single ATAG memory entry but got 0 <at> cycle 0[initState:build/ARM/arch/arm/linux/system.cc, line 133]Memory Usage: 557548 KBytes- ======================================================================== ==============To overcome the above error, I tried giving specific start addr in 'AddrRange', I replacedrange = AddrRange(self.realview.mem_start_addr,size=mdesc.mem()),with the followingrange = AddrRange(Addr(mdesc.mem()),size=mdesc.mem()),orrange = AddrRange(Addr('1MB'),size=mdesc.mem()),I end up with the below error :======================================================================= ===============warn: This is an integrated DRAMsim v2 moduleListening for system connection on port 5900Listening for system connection on port 3456fatal: system.membus has two ports with same range:system.physmem.portsystem.bridge.slave <at> cycle 0[recvRangeChange:build/ARM/mem/bus.cc, line 407]Memory Usage: 554844 KBytes================================================================== ====================We are not sure, how to resolve the above error.FYI, We have a working version (revision 8868) of gem5 integrated with DRAMSim2 (released by Xiangyu Dong). However, we are trying to use the latest version(revision 9197) of Gem5. The code snippet from the working code is below=================================================================== ===================# self.physmem = PhysicalMemory(range = AddrRange(Addr(m5.options.memsize)),# zero = True) self.physmem = DRAMMemory(range = AddrRange(Addr(m5.options.memsize)), zero = True, log_file = os.path.join(m5.options.outdir, "gem5dramsim2"), memory_spec = os.path.join("/archgroup/projects/poweragile/tools/gem5/ext/dramsim2/ini /DDR3_micron_32M_8B_x8_sg15.ini"), mem_clock = m5.options.memclock)#ini/DDR2_micron_32M_8B_x4_sg25E.ini"))============= ======================================================================== =Code looks much similar; however DRAMsim2 wrapper interface, and gem5 to memory interface seem to have changed.Any guidance regarding the above will be very helpful.Thank you-Rizwana > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you._______________________________________________gem5-users mailing listgem5-users <at> gem5.orghttp://m5sim.org/cgi- bin/mailman/listinfo/gem5-users > > Is that error ever resolved ? > > > > _______________________________________________ > gem5-users mailing list > gem5-users <at> gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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