Hi Prathap, That sounds very odd and should not happen unless the workload itself is somehow random. What is it you are running? Are you sure you’re running exactly the same thing?
If it does indeed vary then it would be good if you can track down why by running two simulations in lock-step and determining where they diverge. We regularly run the ARM regressions with UBSan to ensure there is no undefined behaviour in the simulator. I know that for X86 there are quite a few warnings from UBSan, so that could be a reason if you’re using x86. Andreas From: gem5-users <[email protected]<mailto:[email protected]>> on behalf of Prathap Kolakkampadath <[email protected]<mailto:[email protected]>> Reply-To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Thursday, 13 August 2015 09:11 To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Subject: [gem5-users] Sources of In-determinism in Full System Simulators Hello User, I am running a benchmark in gem5 full system mode. Checkpoint is created in atomic mode and then switches to detailed mode before starting the benchmark. On repeated runs of the benchmark from same checkpoint, the number of memory requests arriving at DRAM banks differs; up-to 5% variation. Can someone point out, what could be the sources of in-determinism? Thanks, Prathap -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
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