Hello All, I am trying to modify various width configurations in O3_ARM_v7a.py to simulate pipeline width of 2 (trying to model Cortex-A9). I modified the widths as follows:
fetchWidth = 3 -> 2 decodeWidth = 3 -> 2 renameWidth = 3 -> 2 dispatchWidth = 6 -> 2 issueWidth = 8 -> 2 wbWidth = 8 -> 2 commitWidth = 8 -> 2 squashWidth = 8 -> 2 As I reduced the wbWidth, I ran into the following assertion failure gem5.opt: build/ARM/cpu/timebuf.hh:54: void TimeBuffer<T>::valid(int) const [with T = DefaultIEWDefaultCommit<O3CPUImpl>]: Assertion `idx >= -past && idx <= future' failed. I changed the wbWidth, commitWidth and squashWidth back to 8 (its original value), as the effective width of the pipeline would still be 2 and my simulations were successful. I am curious if anyone has tried to modify the widths (specifically reduce the pipeline width). If so, what is the right way to determine and set write back and commit widths? Thank you, -Rizwana
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