Hi Champs, I poured through the TLB and Table-walker code for ARM architecture... The TLB stores the recent translation. The table-walker helps walk the translation table and arrive at the mapped PA for a VA...
As i understood, the GEM5 code does not seem to implement the page-walk cache. Is my assessment correct? The walker port is connected to the mem-bus. Hence, the walks are not cached in L1D caches, either (that could be an architecture decision). I believe the page-table entries are cached only at L2 level. Is that a correct understanding. Thanks in advance. BR/Nizam
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