Hello. I'm newbie for GEM5.
I want to know the cache performance through various condition on ARM + GEM5 FS
mode.
First time, I just follow the quick start document posted on website and below
command shows the my test environment.
$ build/ARM/gem5.fast configs/example/fs.py --benchmark bbench-ics --
kernel=vmlinux.smp.mouse.arm --frame-capture --num-cpus=4 --cpu-
type=arm_detailed --caches --cacheline_size=64 --l1d_size=32kB --l1d_assoc=4 --
l1i_size=32kB --l1i_assoc=2 --l2cache --l2_size=256kB --l2_assoc=16
After that, I modified the kernel(2.6.35.8-armdroid1+) code for print out cache
information such as CLIDR (Cache Level ID Register) that includes the
information about unified cache or not.
------------------------------------------------------------------------
460 printk("before CLIDR = %x\n", CLIDR);
461 printk("before CCSIDR = %x\n", CCSIDR);
462
463 asm volatile(
464 "mrc p15, 1, %0, c0, c0, 1 \n"
465 :"=r" (CLIDR)
466 :
467 : "cc"
468 );
469
470 asm volatile(
471 "mrc p15, 1, %0, c0, c0, 0 \n"
472 :"=r" (CCSIDR)
473 :
474 : "cc"
475 );
476
477 printk("CLIDR = %x\n", CLIDR);
478 printk("CCSIDR = %x\n", CCSIDR);
------------------------------------------------------------------------
However, the result always shows 0x200000 even if I changed any cache settings.
------------------------------------------------------------------------
<6>CPU: Testing write buffer coherency: ok
<6>How many times execute in loop 32
<6>How many times execute in loop 32
CPU1: Booted secondary processor
<6>How many times execute in loop 32
CPU2: Booted secondary processor
<6>How many times execute in loop 32
CPU3: Booted secondary processor
<6>Brought up 4 CPUs
<6>SMP: Total of 4 processors activated (15990.78 BogoMIPS).
before CLIDR = 0
before CCSIDR = 0
CLIDR = 200000
CCSIDR = 0
------------------------------------------------------------------------
In this case, OS can correctly recognize the cache information? or User have to
change any register setting in GEM5 source code instead of command option?
Thanks.
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