Andreas Hansson <Andreas.Hansson <at> arm.com> writes:

> 
> Hi Ashif,
> 
> I am not too familiar with the x86 system configs in gem5, but if I
> remember correctly there is a 3 GB “hole” in the memory map where the
> first 3 GB goes, and then the remainder goes in some upper address (above
> 32 bit). The consequence is that you get two distinct memory ranges, and
> each range gets as many channels as you have specified. Thus, in your case
> you have 8 channels(!).
> 
> The other part is the use of large simulated memories. By default gem5
> calls mmap in such a way that the host machine has to guarantee swap
> space. You can try and run without this by changing the System parameter
> mmap_noreserve. I have successfully seen simulation runs with many Tbyte
> of memory per socket using this technique. As long as you don’t touch all
> the memory in the guest this should work.
> 
> Andreas
> 
> On 18/09/2015 01:14, "gem5-users on behalf of Ashif Sikder"
> <gem5-users-bounces <at> gem5.org on behalf of ms047914 <at> ohio.edu> wrote:
> 
> >Hi all,
> >
> >I'm new to Gem5. When I try to run Gem5 in Full System mode for x86
> >architecture with --mem-size=16GB, on the master terminal I get:
> >
> >"warn: Physical memory size specified is 16GB which is greater than 3GB.
> >Twice the number of memory controllers would be created."
> >
> >and simulation gets aborted after showing (on the master terminal):
> >
> >"fatal: Could not mmap 13958643712 bytes for range [0x100000000 :
> >0x43fffffff]!".
> >
> >In case of --mem-size=8GB, I get the same warning (on the master
> >terminal):
> >"warn: Physical memory size specified is 8GB which is greater than 3GB.
> >Twice the number of memory controllers would be created."
> >
> >but it runs and after showing:
> >
> >"Initializing CPU#0
> >Checking aperture...
> >No AGP bridge found
> >PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
> >Placing 64MB software IO TLB between ffff880020000000 - ffff880024000000
> >software IO TLB at phys 0x20000000 - 0x24000000
> >Memory: 8183752k/9437184k available (4469k kernel code, 1048964k absent,
> >203544k reserved, 2815k data, 376k init)"
> >
> >on the slave terminal simulation gets aborted.
> >
> >I have looked into the discussion at
> >http://comments.gmane.org/gmane.comp.emulators.m5.users/17539  and the
> >source code at /configs/common/FSConfig.py but could not solve the
> >problem.
> >
> >The command line used is:
> >
> >./build/X86/gem5-MESI2L.opt ./configs/example/fs.py
> >--disk-image=linux-x86.img --kernel=x86-vmlinux-2.6.22.9.smp
> >--cpu-type=timing --ruby --num-cpus=16 --mesh-rows=4 --num-dirs=4
> >--mem-type=DDR4_2400_x64 --mem-channels=4 --mem-size=8GB
> >--topology=MeshDirCorners
> >
> >Any help will be highly appreciated. Thanks.
> >
> >_______________________________________________
> >gem5-users mailing list
> >gem5-users <at> gem5.org
> >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
> 
> 
> ________________________________
> 



Hi Andreas,

Thanks for your reply. 

I am having hard time to find the system parameter "mmap_noreserve". Can you
give some more information?

If I understand things correctly, the on-chip routers are connected using
IntLink, cache & directory controllers are connected to routers using
ExtLink. The directory controllers are connected with the memory controllers
and each memory controller is connected with a memory channel. Right?

If there are two distinct memory ranges each with same number of memory
channels, how are they connected with the memory controllers? (Memory
controllers are being doubled too!?). 

https://www.mail-archive.com/[email protected]/msg12225.html

According to the above thread, multiple memory controllers can be connected
with a directory controller. This might be a naive question, 

can multiple directory controllers be connected with a memory controller and
can multiple routers be connected with a directory controller?

And in the command line I used 

"-num-dirs=4 --mem-channels=4" 

but when I looked into the  config.json  file, there were one  "mem_ctrls"
with  "channels": 1.  So, my last question will be, 

when we define the number of directories and number of channels, how do they
get assigned?

I appreciate your help. Thanks.
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