Hi Dhaval, I am not sure what your "LPDDR4 DRAM memory component" meant. If you refers to an LPDDR4 controller model, the answer is *yes*. Gem5's memory controller supports the basic features of LPDDR4. It already provides you the default LPDDR3's timing. You can start from it with necessary modifications. Note that the per-bank refresh is not supported yet. If that's a "must-be" feature in your design, you may need to add some codes. (also, it doesn't model the multi-cycle commands, but in most cases it should have little impact on your performance evaluation.)
If you are asking whether there is an LPDDR4 DRAM device model that can accepts the commands issued by your verilog controller, the answer is *no*. Gem5 is a SW timing model but can't recognize any real signals from RTL design. -Tao On Wed, Sep 23, 2015 at 9:43 PM, Dhaval Shah <[email protected]> wrote: > Hello, > > > > I am new to gem5 and wanted to know does gem5 supports LPDDR4 DRAM memory > component. We have LPDDR4 memory controller developed in Verilog. > > Can I exercise traffic via gem5 if supported? > > > > Dhaval > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
