Thanks Tao. One more question : If I have LPDDR4 Memory Controller developed in SystemC, will it work with gem5?
Dhaval On Thu, Sep 24, 2015 at 9:30 PM, <[email protected]> wrote: > Send gem5-users mailing list submissions to > [email protected] > > To subscribe or unsubscribe via the World Wide Web, visit > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > or, via email, send a message with subject or body 'help' to > [email protected] > > You can reach the person managing the list at > [email protected] > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of gem5-users digest..." > > > Today's Topics: > > 1. Re: Physical memory size is greater than 3GB. Twice the > number of memory controllers would be created. (Ashif Sikder) > 2. LPDDR4 SDRAM support in gem5? (Dhaval Shah) > 3. Re: LPDDR4 SDRAM support in gem5? (Tao Zhang) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Wed, 23 Sep 2015 16:06:10 +0000 (UTC) > From: Ashif Sikder <[email protected]> > To: [email protected] > Subject: Re: [gem5-users] Physical memory size is greater than 3GB. > Twice the number of memory controllers would be created. > Message-ID: <[email protected]> > Content-Type: text/plain; charset=utf-8 > > Andreas Hansson <Andreas.Hansson <at> arm.com> writes: > > > > > Hi Ashif, > > > > I am not too familiar with the x86 system configs in gem5, but if I > > remember correctly there is a 3 GB “hole” in the memory map where the > > first 3 GB goes, and then the remainder goes in some upper address (above > > 32 bit). The consequence is that you get two distinct memory ranges, and > > each range gets as many channels as you have specified. Thus, in your > case > > you have 8 channels(!). > > > > The other part is the use of large simulated memories. By default gem5 > > calls mmap in such a way that the host machine has to guarantee swap > > space. You can try and run without this by changing the System parameter > > mmap_noreserve. I have successfully seen simulation runs with many Tbyte > > of memory per socket using this technique. As long as you don’t touch all > > the memory in the guest this should work. > > > > Andreas > > > > On 18/09/2015 01:14, "gem5-users on behalf of Ashif Sikder" > > <gem5-users-bounces <at> gem5.org on behalf of ms047914 <at> ohio.edu> > wrote: > > > > >Hi all, > > > > > >I'm new to Gem5. When I try to run Gem5 in Full System mode for x86 > > >architecture with --mem-size=16GB, on the master terminal I get: > > > > > >"warn: Physical memory size specified is 16GB which is greater than 3GB. > > >Twice the number of memory controllers would be created." > > > > > >and simulation gets aborted after showing (on the master terminal): > > > > > >"fatal: Could not mmap 13958643712 bytes for range [0x100000000 : > > >0x43fffffff]!". > > > > > >In case of --mem-size=8GB, I get the same warning (on the master > > >terminal): > > >"warn: Physical memory size specified is 8GB which is greater than 3GB. > > >Twice the number of memory controllers would be created." > > > > > >but it runs and after showing: > > > > > >"Initializing CPU#0 > > >Checking aperture... > > >No AGP bridge found > > >PCI-DMA: Using software bounce buffering for IO (SWIOTLB) > > >Placing 64MB software IO TLB between ffff880020000000 - ffff880024000000 > > >software IO TLB at phys 0x20000000 - 0x24000000 > > >Memory: 8183752k/9437184k available (4469k kernel code, 1048964k absent, > > >203544k reserved, 2815k data, 376k init)" > > > > > >on the slave terminal simulation gets aborted. > > > > > >I have looked into the discussion at > > >http://comments.gmane.org/gmane.comp.emulators.m5.users/17539 and the > > >source code at /configs/common/FSConfig.py but could not solve the > > >problem. > > > > > >The command line used is: > > > > > >./build/X86/gem5-MESI2L.opt ./configs/example/fs.py > > >--disk-image=linux-x86.img --kernel=x86-vmlinux-2.6.22.9.smp > > >--cpu-type=timing --ruby --num-cpus=16 --mesh-rows=4 --num-dirs=4 > > >--mem-type=DDR4_2400_x64 --mem-channels=4 --mem-size=8GB > > >--topology=MeshDirCorners > > > > > >Any help will be highly appreciated. Thanks. > > > > > >_______________________________________________ > > >gem5-users mailing list > > >gem5-users <at> gem5.org > > >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > > ________________________________ > > > > > > Hi Andreas, > > Thanks for your reply. > > I am having hard time to find the system parameter "mmap_noreserve". Can > you > give some more information? > > If I understand things correctly, the on-chip routers are connected using > IntLink, cache & directory controllers are connected to routers using > ExtLink. The directory controllers are connected with the memory > controllers > and each memory controller is connected with a memory channel. Right? > > If there are two distinct memory ranges each with same number of memory > channels, how are they connected with the memory controllers? (Memory > controllers are being doubled too!?). > > https://www.mail-archive.com/[email protected]/msg12225.html > > According to the above thread, multiple memory controllers can be connected > with a directory controller. This might be a naive question, > > can multiple directory controllers be connected with a memory controller > and > can multiple routers be connected with a directory controller? > > And in the command line I used > > "-num-dirs=4 --mem-channels=4" > > but when I looked into the config.json file, there were one "mem_ctrls" > with "channels": 1. So, my last question will be, > > when we define the number of directories and number of channels, how do > they > get assigned? > > I appreciate your help. Thanks. > > ------------------------------ > > Message: 2 > Date: Thu, 24 Sep 2015 10:13:31 +0530 > From: "Dhaval Shah" <[email protected]> > To: <[email protected]> > Subject: [gem5-users] LPDDR4 SDRAM support in gem5? > Message-ID: <[email protected]> > Content-Type: text/plain; charset="utf-8" > > Hello, > > > > I am new to gem5 and wanted to know does gem5 supports LPDDR4 DRAM memory > component. We have LPDDR4 memory controller developed in Verilog. > > Can I exercise traffic via gem5 if supported? > > > > Dhaval > > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: < > http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20150924/068bfc9c/attachment-0001.html > > > > ------------------------------ > > Message: 3 > Date: Wed, 23 Sep 2015 22:49:57 -0700 > From: Tao Zhang <[email protected]> > To: gem5 users mailing list <[email protected]> > Subject: Re: [gem5-users] LPDDR4 SDRAM support in gem5? > Message-ID: > <CABJ3yzK1GX_hp+gQ9bQ4vH9s3kWx2= > [email protected]> > Content-Type: text/plain; charset="utf-8" > > Hi Dhaval, > > I am not sure what your "LPDDR4 DRAM memory component" meant. If you refers > to an LPDDR4 controller model, the answer is *yes*. Gem5's memory > controller supports the basic features of LPDDR4. It already provides you > the default LPDDR3's timing. You can start from it with necessary > modifications. Note that the per-bank refresh is not supported yet. If > that's a "must-be" feature in your design, you may need to add some codes. > (also, it doesn't model the multi-cycle commands, but in most cases it > should have little impact on your performance evaluation.) > > If you are asking whether there is an LPDDR4 DRAM device model that can > accepts the commands issued by your verilog controller, the answer is *no*. > Gem5 is a SW timing model but can't recognize any real signals from RTL > design. > > -Tao > > On Wed, Sep 23, 2015 at 9:43 PM, Dhaval Shah < > [email protected]> > wrote: > > > Hello, > > > > > > > > I am new to gem5 and wanted to know does gem5 supports LPDDR4 DRAM memory > > component. We have LPDDR4 memory controller developed in Verilog. > > > > Can I exercise traffic via gem5 if supported? > > > > > > > > Dhaval > > > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: < > http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20150923/b9c13310/attachment-0001.html > > > > ------------------------------ > > Subject: Digest Footer > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ------------------------------ > > End of gem5-users Digest, Vol 110, Issue 20 > ******************************************* >
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