Hi all, I am working on instantiating a DRAM LLC (currently just L2) in gem5 classic memory module. I am currently use DRAM cache with SRAM tag array and hence just need the DRAM timing latency rather than fixed hit latency of SRAM. Since instantiating multiple object of DRAMCtrl contributes directly to main memory, I decide to do the following
1. instantiate DRAMCtrl as normal memory controller. 2. Instantiate DRAMSim2 as DRAM l2 cache with another l2 tag cache array by inheriting the same from MemObject rather than abstract memory. Some other minute changes are also there. 3. I connect the tag array to the DRAMSim2 with a non coherent bus using a separate port known as array side port in the DRAM cache 4. I added the code in cache_impl(diff attached) 5. I have asso modified CacheConfig.py accordingly. Every thing seems to be OK. As I start the simulation, I observe that there are transaction on the new bus to the DRAM cache but the simulation hangs after a few transactions. I understand that I am doing some mistake in handling the request which are hit in the cache but unable to figure out what is the bug. I have worked fair bit on DRAM Controllers but this is my first experience with caches in gem5. I have also attached the dot file generated by gem5. Thanks, Debiprasanna Sahoo
cache_diff
Description: Binary data
config.dot.pdf
Description: Adobe PDF document
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