Hello Andreas, Thanks for your reply.
Prathap On Mon, Nov 9, 2015 at 1:27 PM, Andreas Hansson <[email protected]> wrote: > Hi Prathap, > > Command-bus contention is intentionally not modelled. The main reason for > this is to keep the model performant. Moreover, in real devices the command > bus is typically designed to _not_ be a bottleneck. Admittedly this choice > could be reassessed if needed. > > Andreas > > From: gem5-users <[email protected]> on behalf of Prathap > Kolakkampadath <[email protected]> > Reply-To: gem5 users mailing list <[email protected]> > Date: Monday, 9 November 2015 at 18:25 > To: gem5 users mailing list <[email protected]> > Subject: [gem5-users] Modelling command bus contention in DRAM controller > > > Hello Users, > > After closely looking at the doDRAMAccess() of dram controller > implementation in GEM5, i suspect that the current implementation may not > be taking in to account the command bus contention that could happen if > DRAM timing constraints take particular values. > > For example in the below scenario, the queue has two closed requests one > to Bank1 and other to Bank2. > > Request1@Bank1 (PRE-ACT-CAS) --> Request2@Bank2 (PRE-ACT-CAS) > > Lets say tRP(8cycles), tRCD(8cycles), tCL(8cycles), and tRRD(8 cycles). In > this case ACT of R2 and CAS of R1 becomes active at the same time. > At this point one command needs to be delayed by one clock cycle. I don't > see how simulator is handling this? If the simulator is handling this, > could someone please point me to the code snippet where this is handled. > > > Thanks, > Prathap > > > ------------------------------ > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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