Hi Andreas;
I installed pydot. Now am more clear with the topology. I want to put the
monitor "before L2". So, tried changing BaseCPU.py as:
#self.toL2Bus.master = self.l2cache.cpu_side
self.monitor = CommMonitor()
self.monitor.StackDist = StackDistProbe(verify = True)
self.toL2Bus.master = self.monitor.slave
self.monitor.master = self.l2cache.cpu_side
self._cached_ports = ['l2cache.mem_side']
I recompiled and and trier to run an example and received error as:
fatal: system.monitor.stackdist without default or user set value
And I also cannot see the CommMonitor anywhere in the in the dot files.
Do I also need to make change in se.py and CommMonitor.py??? I have
attached the three files for reference.
Thanks,
Bhaskar
On Sun, Nov 8, 2015 at 10:34 PM, Andreas Hansson <[email protected]>
wrote:
> Hi Bhaskar,
>
> Something is not quite right in the topology you are expressing in these
> lines. Have you looked at the graphical output (make sure you have py-dot
> installed)?
>
> You want to trace _after_ the l2? If so, I would suggest to connect the L2
> cache as usual. Then instantiate and connect the monitor:
>
> self.monitor = CommMonitor()
> self.monitor.slave = self.l2cache.mem_side
> self._cached_ports = [‘monitor.master’]
>
> This will leave the CommMonitor as the “exposed” port being connected
> downwards.
>
> Make sure this is all working before you start fiddling with the probes.
> The graphical output is your friend…
>
> Once the above is working, it should just be a matter of adding a line:
>
> self.monitor.sdprobe = StackDistProbe()
>
> Andreas
>
> From: gem5-users <[email protected]> on behalf of Bhaskar
> Kalita <[email protected]>
> Reply-To: gem5 users mailing list <[email protected]>
> Date: Sunday, 8 November 2015 at 12:16
>
> To: gem5 users mailing list <[email protected]>
> Subject: Re: [gem5-users] How to use stack distance calculator in gem5.
>
> Hi Andreas,
>
> You did not respond to my previous mail, hope you reply to this. I went
> through the mail archive regarding CommMonitor. I tried again changing
> BaseCPU.py as:
>
> self.toL2Bus.master = self.l2cache.cpu_side
> self._cached_ports = ['l2cache.mem_side']
> self.monitor = CommMonitor()
> self.monitor.stackdist = StackDistProbe(verify = True)
> self.l2cache.cpu_side = self.monitor.master
> self.monitor.slave = self.l2cache.mem_side
>
> I re-compiled and tried to run an example but received the following error:
>
> fatal: system.monitor.stackdist without default or user set value
>
> For reference my command line was:
>
> build/X86/gem5.debug --debug-flag=StackDist --stats-file=hello.txt
> --dump-config=hello.ini --json-config=hello.json configs/example/se.py
> --num-cpus=1 --cpu-type=DerivO3CPU --caches --l1i_size=32kB --l1d_size=32kB
> --l2cache --num-l2caches=1 --l2_size=256kB --l2_assoc=4 -c
> 'tests/test-progs/hello/bin/x86/linux/hello;'
>
> Can you help me out where am making the mistake.
>
> Thanks,
> Bhaskar
>
>
>
>
>
> On Fri, Nov 6, 2015 at 5:03 AM, Bhaskar Kalita <[email protected]>
> wrote:
>
>> Hi Andreas
>>
>> I want to measure the stack distance for l2 cache. So, tried to place the
>> CommMonitor between toL2Bus.master and l2cache.cpu_side in BaseCPU.py as:
>>
>> #self.toL2Bus.master = self.l2cache.cpu_side
>> #self._cached_ports = ['l2cache.mem_side']
>> self.l2MONITOR = CommMonitor()
>> self.l2MONITOR.stackdist = StackDistProbe(verify = True)
>> self.toL2Bus.master = self.l2MONITOR.slave
>> self.l2MONITOR.master = self.l2cache.cpu_side
>> self._cached_ports = ['l2cache.mem_side']
>>
>> I tried assigning a StackDistProbe to the comm monitor as:
>>
>> stackdist = Param.StackDistProbe(NULL)
>>
>> I re-compiled as scons build/X86/gem5.debug. It worked fine. The error I
>> got while trying to run an example was
>>
>> Traceback (most recent call last):
>> File "<string>", line 1, in <module>
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/src/python/m5/main.py",
>> line 389, in main
>> exec filecode in scope
>> File "configs/example/se.py", line 286, in <module>
>> Simulation.run(options, root, system, FutureClass)
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/configs/common/Simulation.py",
>> line 583, in run
>> m5.instantiate(checkpoint_dir)
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/src/python/m5/simulate.py",
>> line 114, in instantiate
>> for obj in root.descendants(): obj.createCCObject()
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/src/python/m5/SimObject.py",
>> line 1453, in createCCObject
>> self.getCCParams()
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/src/python/m5/SimObject.py",
>> line 1400, in getCCParams
>> value = value.getValue()
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/src/python/m5/SimObject.py",
>> line 1457, in getValue
>> return self.getCCObject()
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/src/python/m5/SimObject.py",
>> line 1435, in getCCObject
>> params = self.getCCParams()
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/src/python/m5/SimObject.py",
>> line 1400, in getCCParams
>> value = value.getValue()
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/src/python/m5/params.py",
>> line 248, in getValue
>> return [ v.getValue() for v in self ]
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/src/python/m5/SimObject.py",
>> line 1457, in getValue
>> return self.getCCObject()
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/src/python/m5/SimObject.py",
>> line 1435, in getCCObject
>> params = self.getCCParams()
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/src/python/m5/SimObject.py",
>> line 1400, in getCCParams
>> value = value.getValue()
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/src/python/m5/SimObject.py",
>> line 1457, in getValue
>> return self.getCCObject()
>> File
>> "/home/bhaskar/Downloads/gem5-stable-a48faafdb3bf/src/python/m5/SimObject.py",
>> line 1439, in getCCObject
>> % self.path()
>> RuntimeError: system.monitor.stackdist: Cycle found in configuration
>> hierarchy.
>>
>>
>> Can you please explain if I need to modify se.py for my purpose? Please
>> help me out through this as I am very new to gem5.
>>
>>
>> Thanks
>>
>> Bhaskar
>>
>>
>>
>>
>>
>> On Thu, Nov 5, 2015 at 1:50 PM, Andreas Hansson <[email protected]>
>> wrote:
>>
>>> Hi Bhaskar,
>>>
>>> Have a look at tests/config/tgen-simple-mem.py.
>>>
>>> The comm monitor has a master and a slave port, and you need to connect
>>> it “between” two other modules. There are plenty examples on the mailing
>>> list for adding it between the L1 and L2, for example by changing
>>> BaseCpu.py (if you do, remember to recompile). Once you have instantiated
>>> the comm monitor, and connected it, run an experiment and make sure you get
>>> the stats in the stats.txt output. Also, if you install pydot, you can see
>>> the system topology in m5out/config.dot.pdf or config.dot.svg (the latter
>>> even has mouseover tooltips etc).
>>>
>>> When the things above are working, just assign a StackDistProbe to the
>>> comm monitor, as done in tests/config/tgen-simple-mem.py.
>>>
>>> Good luck.
>>>
>>> Andreas
>>>
>>> From: gem5-users <[email protected]> on behalf of Bhaskar
>>> Kalita <[email protected]>
>>> Reply-To: gem5 users mailing list <[email protected]>
>>> Date: Wednesday, 4 November 2015 at 20:23
>>> To: gem5 users mailing list <[email protected]>
>>> Subject: Re: [gem5-users] How to use stack distance calculator in gem5.
>>>
>>> Hi Andreas,
>>>
>>> Thanks for your response. Can you please tell me how to instantiate the
>>> probe. I tried modifying the se.py file as:
>>>
>>> # Create a separate clock domain for the CPUs
>>> system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
>>> voltage_domain =
>>> system.cpu_voltage_domain)
>>>
>>> # to calculate stack distance
>>> system.monitor = CommMonitor()
>>> system.monitor.stackdist = StackDistProbe(verify = True)
>>>
>>>
>>> And also changed BaseCPU.py as:
>>>
>>> def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
>>> self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
>>> self.toL2Bus = L2XBar()
>>> self.connectCachedPorts(self.toL2Bus)
>>> self.l2cache = l2c
>>> self.toL2Bus.master = self.l2cache.cpu_side
>>> self._cached_ports = ['l2cache.mem_side']
>>>
>>> # to calculate stack distance
>>> self.l2MONITOR = StackDistProbe(verify = True)
>>> self._cached_ports = self.l2MONITOR.slave
>>> self.l2MONITOR.master = l2cache.mem_side
>>>
>>> When I tried to run my program I got an error as "fatal: Communication
>>> monitor is not connected on both sides."
>>> Can you please tell me if I am approaching in the right direction and
>>> what are the other things to be done.
>>>
>>> Thanks
>>>
>>>
>>>
>>> On Mon, Nov 2, 2015 at 2:10 PM, Andreas Hansson <[email protected]
>>> > wrote:
>>>
>>>> Hi Bhaskar,
>>>>
>>>> There are a few steps you need to take, and it involves a few
>>>> widely-adopted gem5 concepts:
>>>>
>>>> - First, the stack distance calculator is a probe, and the output is in
>>>> the shape of gem5 stats. Thus, you need to instantiate the probe, and
>>>> attach it to a probe point.
>>>>
>>>> - Second, to be able to attach the probe in various locations in the
>>>> memory system (core to L1, before the L2, in front of the system memory),
>>>> we use a module called a CommMonitor, which has a bunch of generic stats,
>>>> but also suitable packet probe points.
>>>>
>>>> Consequently, you need to modify your script that assembles and
>>>> configures the system, in your case se.py, and instantiate a CommMonitor,
>>>> connect it where you want to monitor the communication, then instantiate a
>>>> StackDistProbe and attach it to the monitor you just instantiated. The bad
>>>> news is that it involves quite a few steps. The good news is that these are
>>>> all things you will need to do as a gem5 user in any case, so better get
>>>> used to it :-).
>>>>
>>>> For an example, have a look at one of the regression scripts,
>>>> tests/config/tgen-simple-mem.py. This script includes both trace
>>>> generation, and calculation of stack distance. Note that you don’t need to
>>>> set "verify = True" on the StackDistProbe. If you do you will calculate the
>>>> stack distance both using a clever algorithm, and a “naïve” stack which is
>>>> a lot slower.
>>>>
>>>> Andreas
>>>>
>>>>
>>>> From: gem5-users <[email protected]> on behalf of Bhaskar
>>>> Kalita <[email protected]>
>>>> Reply-To: gem5 users mailing list <[email protected]>
>>>> Date: Sunday, 1 November 2015 at 22:08
>>>> To: "[email protected]" <[email protected]>
>>>> Subject: [gem5-users] How to use stack distance calculator in gem5.
>>>>
>>>> Hi
>>>> I am Bhaskar. I am a final year B.E student. For my final year project
>>>> I am using the gem5 simulator. I need to collect the stack distance of
>>>> programs using gem5. I used the --debug-flag="StackDist", but it did not
>>>> print anything. I also tried setting the verifyStack flag in
>>>> mem/stack_dist_calc.hh to true as:
>>>> // Flag to enable verification of stack. (Slows down the simulation)
>>>> const bool verifyStack=true;
>>>> but it did not work too. For reference this is the command line am
>>>> usuing:
>>>> build/X86/gem5.debug --debug-flag='StackDist' --debug-file='sdp.trc.gz'
>>>> --stats-file=forij.txt --dump-config=for.ini --json-config=for.json
>>>> configs/example/se.py --num-cpus=1 --cpu-type=DerivO3CPU --caches
>>>> --l1i_size=32kB --l1d_size=32kB --l2cache --num-l2caches=1 --l2_size=256kB
>>>> --l2_assoc=4 -c "bench/x86/forij;"
>>>>
>>>> Can you please guide me through my problem and tell me to do the
>>>> necessary steps.
>>>>
>>>> Thanks for your support
>>>>
>>>> -Bhaskar
>>>>
>>>>
>>>>
>>>> ------------------------------
>>>>
>>>> -- IMPORTANT NOTICE: The contents of this email and any attachments are
>>>> confidential and may also be privileged. If you are not the intended
>>>> recipient, please notify the sender immediately and do not disclose the
>>>> contents to any other person, use it for any purpose, or store or copy the
>>>> information in any medium. Thank you.
>>>>
>>>> _______________________________________________
>>>> gem5-users mailing list
>>>> [email protected]
>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>>
>>>
>>>
>>> ------------------------------
>>>
>>> -- IMPORTANT NOTICE: The contents of this email and any attachments are
>>> confidential and may also be privileged. If you are not the intended
>>> recipient, please notify the sender immediately and do not disclose the
>>> contents to any other person, use it for any purpose, or store or copy the
>>> information in any medium. Thank you.
>>>
>>> _______________________________________________
>>> gem5-users mailing list
>>> [email protected]
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>
>>
>
> ------------------------------
>
> -- IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
>
> _______________________________________________
> gem5-users mailing list
> [email protected]
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
# Copyright (c) 2012-2013, 2015 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2005-2008 The Regents of The University of Michigan
# Copyright (c) 2011 Regents of the University of California
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
# Rick Strong
# Andreas Hansson
import sys
from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
from XBar import L2XBar
from InstTracer import InstTracer
from CPUTracers import ExeTracer
from MemObject import MemObject
from ClockDomain import *
default_tracer = ExeTracer()
if buildEnv['TARGET_ISA'] == 'alpha':
from AlphaTLB import AlphaDTB, AlphaITB
from AlphaInterrupts import AlphaInterrupts
from AlphaISA import AlphaISA
isa_class = AlphaISA
elif buildEnv['TARGET_ISA'] == 'sparc':
from SparcTLB import SparcTLB
from SparcInterrupts import SparcInterrupts
from SparcISA import SparcISA
isa_class = SparcISA
elif buildEnv['TARGET_ISA'] == 'x86':
from X86TLB import X86TLB
from X86LocalApic import X86LocalApic
from X86ISA import X86ISA
isa_class = X86ISA
elif buildEnv['TARGET_ISA'] == 'mips':
from MipsTLB import MipsTLB
from MipsInterrupts import MipsInterrupts
from MipsISA import MipsISA
isa_class = MipsISA
elif buildEnv['TARGET_ISA'] == 'arm':
from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
from ArmInterrupts import ArmInterrupts
from ArmISA import ArmISA
isa_class = ArmISA
elif buildEnv['TARGET_ISA'] == 'power':
from PowerTLB import PowerTLB
from PowerInterrupts import PowerInterrupts
from PowerISA import PowerISA
isa_class = PowerISA
class BaseCPU(MemObject):
type = 'BaseCPU'
abstract = True
cxx_header = "cpu/base.hh"
@classmethod
def export_methods(cls, code):
code('''
void switchOut();
void takeOverFrom(BaseCPU *cpu);
bool switchedOut();
void flushTLBs();
Counter totalInsts();
void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
''')
@classmethod
def memory_mode(cls):
"""Which memory mode does this CPU require?"""
return 'invalid'
@classmethod
def require_caches(cls):
"""Does the CPU model require caches?
Some CPU models might make assumptions that require them to
have caches.
"""
return False
@classmethod
def support_take_over(cls):
"""Does the CPU model support CPU takeOverFrom?"""
return False
def takeOverFrom(self, old_cpu):
self._ccObject.takeOverFrom(old_cpu._ccObject)
system = Param.System(Parent.any, "system object")
cpu_id = Param.Int(-1, "CPU identifier")
socket_id = Param.Unsigned(0, "Physical Socket identifier")
numThreads = Param.Unsigned(1, "number of HW thread contexts")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Tick to start function trace")
checker = Param.BaseCPU(NULL, "checker CPU")
do_checkpoint_insts = Param.Bool(True,
"enable checkpoint pseudo instructions")
do_statistics_insts = Param.Bool(True,
"enable statistics pseudo instructions")
profile = Param.Latency('0ns', "trace the kernel stack")
do_quiesce = Param.Bool(True, "enable quiesce instructions")
workload = VectorParam.Process([], "processes to run")
if buildEnv['TARGET_ISA'] == 'sparc':
dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
interrupts = VectorParam.SparcInterrupts(
[], "Interrupt Controller")
isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'alpha':
dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
interrupts = VectorParam.AlphaInterrupts(
[], "Interrupt Controller")
isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'x86':
dtb = Param.X86TLB(X86TLB(), "Data TLB")
itb = Param.X86TLB(X86TLB(), "Instruction TLB")
interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'mips':
dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
interrupts = VectorParam.MipsInterrupts(
[], "Interrupt Controller")
isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'arm':
dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
interrupts = VectorParam.ArmInterrupts(
[], "Interrupt Controller")
isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'power':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
interrupts = VectorParam.PowerInterrupts(
[], "Interrupt Controller")
isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
else:
print "Don't know what TLB to use for ISA %s" % \
buildEnv['TARGET_ISA']
sys.exit(1)
max_insts_all_threads = Param.Counter(0,
"terminate when all threads have reached this inst count")
max_insts_any_thread = Param.Counter(0,
"terminate when any thread reaches this inst count")
simpoint_start_insts = VectorParam.Counter([],
"starting instruction counts of simpoints")
max_loads_all_threads = Param.Counter(0,
"terminate when all threads have reached this load count")
max_loads_any_thread = Param.Counter(0,
"terminate when any thread reaches this load count")
progress_interval = Param.Frequency('0Hz',
"frequency to print out the progress message")
switched_out = Param.Bool(False,
"Leave the CPU switched out after startup (used when switching " \
"between CPU models)")
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
icache_port = MasterPort("Instruction Port")
dcache_port = MasterPort("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
_cached_ports += ["itb.walker.port", "dtb.walker.port"]
_uncached_slave_ports = []
_uncached_master_ports = []
if buildEnv['TARGET_ISA'] == 'x86':
_uncached_slave_ports += ["interrupts[0].pio",
"interrupts[0].int_slave"]
_uncached_master_ports += ["interrupts[0].int_master"]
def createInterruptController(self):
if buildEnv['TARGET_ISA'] == 'sparc':
self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)]
elif buildEnv['TARGET_ISA'] == 'alpha':
self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)]
elif buildEnv['TARGET_ISA'] == 'x86':
self.apic_clk_domain = DerivedClockDomain(clk_domain =
Parent.clk_domain,
clk_divider = 16)
self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain,
pio_addr=0x2000000000000000)
for i in xrange(self.numThreads)]
_localApic = self.interrupts
elif buildEnv['TARGET_ISA'] == 'mips':
self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
elif buildEnv['TARGET_ISA'] == 'arm':
self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
elif buildEnv['TARGET_ISA'] == 'power':
self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
else:
print "Don't know what Interrupt Controller to use for ISA %s" % \
buildEnv['TARGET_ISA']
sys.exit(1)
def connectCachedPorts(self, bus):
for p in self._cached_ports:
exec('self.%s = bus.slave' % p)
def connectUncachedPorts(self, bus):
for p in self._uncached_slave_ports:
exec('self.%s = bus.master' % p)
for p in self._uncached_master_ports:
exec('self.%s = bus.slave' % p)
def connectAllPorts(self, cached_bus, uncached_bus = None):
self.connectCachedPorts(cached_bus)
if not uncached_bus:
uncached_bus = cached_bus
self.connectUncachedPorts(uncached_bus)
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
if iwc and dwc:
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
self.itb.walker.port = iwc.cpu_side
self.dtb.walker.port = dwc.cpu_side
self._cached_ports += ["itb_walker_cache.mem_side", \
"dtb_walker_cache.mem_side"]
else:
self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
# Checker doesn't need its own tlb caches because it does
# functional accesses only
if self.checker != NULL:
self._cached_ports += ["checker.itb.walker.port", \
"checker.dtb.walker.port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
self.toL2Bus = L2XBar()
self.connectCachedPorts(self.toL2Bus)
self.l2cache = l2c
#self.toL2Bus.master = self.l2cache.cpu_side
self.monitor = CommMonitor()
self.monitor.StackDist = StackDistProbe(verify = True)
self.toL2Bus.master = self.monitor.slave
self.monitor.master = self.l2cache.cpu_side
self._cached_ports = ['l2cache.mem_side']
def createThreads(self):
self.isa = [ isa_class() for i in xrange(self.numThreads) ]
if self.checker != NULL:
self.checker.createThreads()
def addCheckerCpu(self):
pass
# Copyright (c) 2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Thomas Grass
# Andreas Hansson
from m5.params import *
from m5.proxy import *
from MemObject import MemObject
from System import System
# The communication monitor will most typically be used in combination
# with periodic dumping and resetting of stats using schedStatEvent
class CommMonitor(MemObject):
type = 'CommMonitor'
cxx_header = "mem/comm_monitor.hh"
system = Param.System(Parent.any, "System that the monitor belongs to.")
# one port in each direction
master = MasterPort("Master port")
slave = SlavePort("Slave port")
# control the sample period window length of this monitor
sample_period = Param.Clock("1ms", "Sample period for histograms")
# for each histogram, set the number of bins and enable the user
# to disable the measurement, reads and writes use the same
# parameters
# histogram of burst length of packets (not using sample period)
burst_length_bins = Param.Unsigned('20', "# bins in burst length " \
"histograms")
disable_burst_length_hists = Param.Bool(False, "Disable burst length " \
"histograms")
# bandwidth per sample period
bandwidth_bins = Param.Unsigned('20', "# bins in bandwidth histograms")
disable_bandwidth_hists = Param.Bool(False, "Disable bandwidth histograms")
# latency from request to response (not using sample period)
latency_bins = Param.Unsigned('20', "# bins in latency histograms")
disable_latency_hists = Param.Bool(False, "Disable latency histograms")
# inter transaction time (ITT) distributions in uniformly sized
# bins up to the maximum, independently for read-to-read,
# write-to-write and the combined request-to-request that does not
# separate read and write requests
itt_bins = Param.Unsigned('20', "# bins in ITT distributions")
itt_max_bin = Param.Latency('100ns', "Max bin of ITT distributions")
disable_itt_dists = Param.Bool(False, "Disable ITT distributions")
# outstanding requests (that did not yet get a response) per
# sample period
outstanding_bins = Param.Unsigned('20', "# bins in outstanding " \
"requests histograms")
disable_outstanding_hists = Param.Bool(False, "Disable outstanding " \
"requests histograms")
# transactions (requests) observed per sample period
transaction_bins = Param.Unsigned('20', "# bins in transaction " \
"count histograms")
disable_transaction_hists = Param.Bool(False, "Disable transaction count " \
"histograms")
# address distributions (heatmaps) with associated address masks
# to selectively only look at certain bits of the address
read_addr_mask = Param.Addr(MaxAddr, "Address mask for read address")
write_addr_mask = Param.Addr(MaxAddr, "Address mask for write address")
disable_addr_dists = Param.Bool(True, "Disable address distributions")
# Stack dist
stackdist = Param.StackDistProbe(NULL)
# Copyright (c) 2012-2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006-2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
# Simple test script
#
# "m5 test.py"
import optparse
import sys
import os
import m5
from m5.defines import buildEnv
from m5.objects import *
from m5.util import addToPath, fatal
addToPath('../common')
addToPath('../ruby')
import Options
import Ruby
import Simulation
import CacheConfig
import MemConfig
from Caches import *
from cpu2000 import *
# Check if KVM support has been enabled, we might need to do VM
# configuration if that's the case.
have_kvm_support = 'BaseKvmCPU' in globals()
def is_kvm_cpu(cpu_class):
return have_kvm_support and cpu_class != None and \
issubclass(cpu_class, BaseKvmCPU)
def get_processes(options):
"""Interprets provided options and returns a list of processes"""
multiprocesses = []
inputs = []
outputs = []
errouts = []
pargs = []
workloads = options.cmd.split(';')
if options.input != "":
inputs = options.input.split(';')
if options.output != "":
outputs = options.output.split(';')
if options.errout != "":
errouts = options.errout.split(';')
if options.options != "":
pargs = options.options.split(';')
idx = 0
for wrkld in workloads:
process = LiveProcess()
process.executable = wrkld
process.cwd = os.getcwd()
if options.env:
with open(options.env, 'r') as f:
process.env = [line.rstrip() for line in f]
if len(pargs) > idx:
process.cmd = [wrkld] + pargs[idx].split()
else:
process.cmd = [wrkld]
if len(inputs) > idx:
process.input = inputs[idx]
if len(outputs) > idx:
process.output = outputs[idx]
if len(errouts) > idx:
process.errout = errouts[idx]
multiprocesses.append(process)
idx += 1
if options.smt:
assert(options.cpu_type == "detailed")
return multiprocesses, idx
else:
return multiprocesses, 1
parser = optparse.OptionParser()
Options.addCommonOptions(parser)
Options.addSEOptions(parser)
if '--ruby' in sys.argv:
Ruby.define_options(parser)
(options, args) = parser.parse_args()
if args:
print "Error: script doesn't take any positional arguments"
sys.exit(1)
multiprocesses = []
numThreads = 1
if options.bench:
apps = options.bench.split("-")
if len(apps) != options.num_cpus:
print "number of benchmarks not equal to set num_cpus!"
sys.exit(1)
for app in apps:
try:
if buildEnv['TARGET_ISA'] == 'alpha':
exec("workload = %s('alpha', 'tru64', '%s')" % (
app, options.spec_input))
elif buildEnv['TARGET_ISA'] == 'arm':
exec("workload = %s('arm_%s', 'linux', '%s')" % (
app, options.arm_iset, options.spec_input))
else:
exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
app, options.spec_input))
multiprocesses.append(workload.makeLiveProcess())
except:
print >>sys.stderr, "Unable to find workload for %s: %s" % (
buildEnv['TARGET_ISA'], app)
sys.exit(1)
elif options.cmd:
multiprocesses, numThreads = get_processes(options)
else:
print >> sys.stderr, "No workload specified. Exiting!\n"
sys.exit(1)
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
CPUClass.numThreads = numThreads
# Check -- do not allow SMT with multiple CPUs
if options.smt and options.num_cpus > 1:
fatal("You cannot use SMT with multiple CPUs!")
np = options.num_cpus
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
mem_mode = test_mem_mode,
mem_ranges = [AddrRange(options.mem_size)],
cache_line_size = options.cacheline_size)
# For CommMonitor
system.monitor = CommMonitor()
#system.monitor.stackdist = StackDistProbe(verify = True)
if numThreads > 1:
system.multi_thread = True
# Create a top-level voltage domain
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = system.voltage_domain)
# Create a CPU voltage domain
system.cpu_voltage_domain = VoltageDomain()
# Create a separate clock domain for the CPUs
system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain =
system.cpu_voltage_domain)
# All cpus belong to a common cpu_clk_domain, therefore running at a common
# frequency.
for cpu in system.cpu:
cpu.clk_domain = system.cpu_clk_domain
if is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass):
if buildEnv['TARGET_ISA'] == 'x86':
system.vm = KvmVM()
for process in multiprocesses:
process.useArchPT = True
process.kvmInSE = True
else:
fatal("KvmCPU can only be used in SE mode with x86")
# Sanity check
if options.fastmem:
if CPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
if options.simpoint_profile:
if not options.fastmem:
# Atomic CPU checked with fastmem option already
fatal("SimPoint generation should be done with atomic cpu and fastmem")
if np > 1:
fatal("SimPoint generation not supported with more than one CPUs")
for i in xrange(np):
if options.smt:
system.cpu[i].workload = multiprocesses
elif len(multiprocesses) == 1:
system.cpu[i].workload = multiprocesses[0]
else:
system.cpu[i].workload = multiprocesses[i]
if options.fastmem:
system.cpu[i].fastmem = True
if options.simpoint_profile:
system.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
system.cpu[i].addCheckerCpu()
system.cpu[i].createThreads()
if options.ruby:
if options.cpu_type == "atomic" or options.cpu_type == "AtomicSimpleCPU":
print >> sys.stderr, "Ruby does not work with atomic cpu!!"
sys.exit(1)
Ruby.create_system(options, False, system)
assert(options.num_cpus == len(system.ruby._cpu_ports))
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
for i in xrange(np):
ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
# in x86 does it have message ports that need to be connected
system.cpu[i].createInterruptController()
# Connect the cpu's cache ports to Ruby
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].interrupts[0].pio = ruby_port.master
system.cpu[i].interrupts[0].int_master = ruby_port.slave
system.cpu[i].interrupts[0].int_slave = ruby_port.master
system.cpu[i].itb.walker.port = ruby_port.slave
system.cpu[i].dtb.walker.port = ruby_port.slave
else:
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
system.system_port = system.membus.slave
CacheConfig.config_cache(options, system)
MemConfig.config_mem(options, system)
root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
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