Hi, I am trying to simulate the ARM system with L1 cache. I can see in config.ini the detailed configuration for dcache and icache, but when I login from m5term and check the cache configuration, I don't see any cache configured.
lscpu output from m5term is the following *root@gem5sim:/sys/devices/system/cpu/cpu0/cpufreq# lscpu* * Architecture: armv7l* * CPU(s): 4* * Thread(s) per core: 1* * Core(s) per socket: 1* * CPU socket(s): 4* Ideally, there should be the entry for l1cache also which seems to be missing. The following is the command that I am using to simulate the system M5_PATH=$(pwd)/.. ./build/ARM/gem5.fast configs/example/fs.py -n 4 *--caches --l1d_size=32kB --l1i_size=32kB* --cpu-type=arm_detailed -r 1 --machine-type=VExpress_EMM --kernel=../linux-linaro-tracking-gem5/vmlinux --dtb-filename=../linux-linaro-tracking-gem5/arch/arm/boot/dts/vexpress-v2p-ca15-tc1-gem5_dvfs_per_core_4cpus.dtb --disk-image=../disks/arm-ubuntu-natty-headless.img --cpu-clock=\['1 GHz','750 MHz','500 MHz'\] So, although I am giving the options to configure the cache, lscpu does not seem to reflect it. Am I missing something in the command? Regards Rahul
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
