Hi All,
For O3 cpu, the rename stage, after encountering a store-conditional
instruction (stxr, stlxr etc), switch to serializing stalls.
Thus all other instructions behind it wait until ROB becomes empty.
To my understanding, instruction like store-exclusive are meant to
provide a sort of atomic read-modify-write operation.
Thus it should not block all the instruction in the pipeline. Am I right here?
Any specific reason for not having Out of Order support for such instructions?
Actually while running dgemm, I found the rename serializing stall
contribute to 33% time of total simulation cycle.
system.cpu.numCycles 80786913
system.cpu.rename.serializeStallCycles 27155716
Thus I want to add this support so that rename does not unnecessary
stalls. Could some one please give high level hint on changes required
to do so.
Below is code snippet (rename_impl.hh) -
// serializeAfter marks the next instruction as serializeBefore.
// serializeBefore makes the instruction wait in rename until the ROB
// is empty.
// In this model, IPR accesses are serialize before
// instructions, and store conditionals are serialize after
// instructions. This is mainly due to lack of support for
// out-of-order operations of either of those classes of
// instructions.
if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
!inst->isSerializeHandled()) {
...
renameStatus[tid] = SerializeStall;
serializeInst[tid] = inst;
blockThisCycle = true;
else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
!inst->isSerializeHandled()) {
renamedSerializing++;
inst->setSerializeHandled();
serializeAfter(insts_to_rename, tid);
}
Thanks in advance for your time.
--
with regards,
Virendra Kumar Pathak
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