-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Hi,
I want to implement two ARM cores in gem5: one Cortex-A53 and one Cortex-A57. I was wondering if it has been already done or if you have some informations about this subject. Thank you. Best regards. +-------------------------------+ | Louisa Bessad | | PhD student - LIRMM - Sysmic | | Bâtiment 4 Bureau H2.2 | +-------------------------------+ -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJWU4RSAAoJEDImrRzYjFZl6XsP/A4H0i7iz65eLC+fcoP9lAYj 2Cb9apHRe91dordlBUrpkTMbpdm+Eqcbj+6DagR/IwxHzrV7TzLz8mol6J9fmIo7 2kj/i+pLPsT/KjSgx56jf6NUK48r999HGG+50IDziV07getaSwvq+4dV3+ck7Wme hmVeNR+HeIfK29o+wq40Gdkviy/3pzQPNrIV1Wp2NM241sPQ78nfkR+xlSOzvv9F vLPruW5sroJ0vkDec2sJENLrTuMzZWg0A26KZQy2H2stQRtQApdouLJ2zRZv3//X 3HvGzS9WW6gmXJaVw6u0toW3gYw+acKjGjnKtOdQm9DZXkPY3ZdguDeWOY36uRR+ Tm/82Tq1WrwMeHAilv5+rT7SbuBPplU1G7yKbBWHM/yG0yM+NqmLQj3/p/PDFEJx 4XCgFU2zktaXmtc5f83Vbc9mi8quQbmBKCLZAV+OKRNHkK32xOkMss5gLtxdSRuQ tr+cN4frxXTSbJxTTVMOLhAdQHph30YeTo5Rd9ScvOJ40pyv0CbyvK3vR1vLKqWA ZCQVS53WT1S9xvbqeXejeI5eSxWdhzh6UcstF2HREDVSYqQEg454bigAulBdJeVz FYgPV8a8arGrnj2Rv9O7DVPPXYzmsca7DVuWWDvK4Gqj7Jxlqmjmj03nSGNAL5XN e/u+TrfvtPUw/LET5+bL =nlbq -----END PGP SIGNATURE----- _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
