Hi all, Currently I'm trying to run the bbench-ics benchmark on Android according to this link : http://www.m5sim.org/BBench-gem5 since yesterday (around 24h), but it hasn't finished its simulation yet. Is this normal? If you have ever tried to run the simulation, how long does it take for you to finish a simulation? I expect the simulation to stop by itself at some time, is this also correct?
Here is the command that I've executed : /path_to_gem5_root/build/ARM/m5.fast configs/example/fs.py -b bbench-ics --kernel=vmlinux.smp.mouse.arm --frame-capture Here is my latest state of my simulation at my terminal : gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. gem5 compiled Nov 24 2015 14:03:59 gem5 started Dec 4 2015 09:23:52 gem5 executing on samsung command line: ./build/ARM/gem5.fast configs/example/fs.py -b bbench-ics --kernel=vmlinux.smp.mouse.arm --frame-capture Global frequency set at 1000000000000 ticks per second info: kernel located at: /path_to_gem5-full-system-images/binaries/vmlinux.smp.mouse.arm Listening for system connection on port 5900 Listening for system connection on port 3456 0: system.remote_gdb.listener: listening for remote gdb on port 7000 info: Using bootloader at address 0x80000000 info: Using kernel entry physical address at 0x8000 **** REAL SIMULATION **** info: Entering event queue @ 0. Starting simulation... warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: The ccsidr register isn't implemented and always reads as 0. warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported Thank you in advance for your time to answer my question. Best Regards, Jeffrey F. Lukman
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