Hello,
I have built SPEC2006 configured with ARM tuned base, tested some benchmarks with two level caches using TimingSimpleCPU model in gem5. The memory system is configured as default two level caches in config/example/se.py and config/commn/CacheConfig.py. But the results shown that CPI was incredibly high, 2.6 for 403.gcc and 5.8 for 429.mcf, for example. Did I miscalculated the CPI which was total cycles divided by sim_ops? If so, what is the right way to estimate the CPI with cache system? I would appreciate for your answer. Regards, Will
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