Hi all, I want to modify gem5 to use it in my computer architecture research. In particular, I want to modify the O3 CPU model and include in it a structure similar to a trace cache.
I have some idea as to where to start, based on other simulators I've already used. My question is whether anyone has done something similar before, and could point me in the right direction (what do I need to understand of the source code first, where will I need to modify the most part, etc.). I thought of defining a new class (the one that behaves similarly to a trace cache) that stores sequences of *StaticInst *that were previously executed together with the initial PC address (encoded in the *PCState * class) of the sequence. Then modify the *DefaultFetch* class to check for any matching entry in the trace cache (current *PCState == *stored *PCState); *if so, then use the stored *StaticInst* list to generate the dynamic instructions (*BaseO3DynInst)* and feed these to the pipeline. Could anyone confirm if this makes sense? Any potention issues I may run into? Thanks in advance! -- Marcelo Brandalero PhD student | Graduate Program in Computer Science Federal University of Rio Grande do Sul Porto Alegre/RS, Brazil
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