AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
what does addr refer to?
The size parameter of this function is equal to the packet size which is
smaller than 64 byte, after writing this packet to a certain line of the
cache, how can I read the whole line where this packet has been already
written?
On Wed, Jan 20, 2016 at 12:24 PM, Arthur Perais <[email protected]>
wrote:
> Le 20/01/2016 12:16, Nour Sayed a écrit :
>
> Dear all,
>
> The cache line size of L1 is by default in Gem5 consists of 64 bytes.
> At the same time, read and write operations in the L1 cache is done using
> packets in the gem5 simulator. Each packet has parameters (main memory
> address, size, data ,....).
> The size of packet is not fixed it can be 1, 4 ,8 ,.. bytes.
>
> My question is, when I write a packet (with size of 1 byte< 64 bytes the
> size of cache line) at a certain line of L1 cache, what will happen to the
> rest of the bytes of that line. What these bytes will have (old data or
> zeros bits or what exactly).
>
>
> As far as I understand, the other bytes will not be modified, which is
> what you would expect.
>
>
> How can I access to a certain line of cache in order to read it?
> When the packets are read or written in the cache, how is the cache line
> in gem5 selected?
>
>
> You can probably use atomic requests with a particular address. It depends
> on what you want to do exactly, I guess. Can you be more specific?
>
> Cheers,
>
> Arthur.
>
> Thanks in advance
> Nour
>
>
>
>
>
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>
> --
> Arthur Perais
> INRIA Bretagne Atlantique
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> 35042 Rennes, France
>
>
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