Hello, I’m trying to simulate a SPARC processor with SMT enabled in SE mode. When I enable the SMT switch (using --smt --cpu-type=detailed --caches) with a single core, it works fine if there’s only one workload. If I add a second workload, though, I get an assertion error that “params->numPhysIntRegs >= numThreads * SparcISA::NumIntRegs” has failed. For reference, the command I’m using to run GEM5 is this:
build/SPARC/gem5.opt configs/example/se.py -c 'tests/test-progs/hello/bin/sparc/linux/hello;tests/test-progs/hello/bin/sparc/linux/hello' --smt --caches --cpu-type=detailed The full error I receive is this: gem5.opt: build/SPARC/cpu/o3/cpu.cc:270: FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams*) [with Impl = O3CPUImpl]: Assertion `params->numPhysIntRegs >= numThreads * SparcISA::NumIntRegs' failed. I looked into the error and it appears that SPARC has 169 integer registers. When multiplied by a numThreads value of 2 from having two workloads, that exceeds the number of physical integer registers available. My understanding was that SPARC had 32 integer registers per hardware thread, but when I change it I get the following error: gem5.opt: build/SPARC/cpu/o3/free_list.hh:68: PhysRegIndex SimpleFreeList::getReg(): Assertion `!freeRegs.empty()' failed. Has anyone gotten SMT to work with SPARC in SE mode? Is there some configuration I’m missing that will make it work? Thanks in advance for your help.
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