Hi Debiprasanna,
I forgot to mention one thing: I used the Hardware Prefetcher. Not only
this, I also changed the default handling for HardPFReq request in the
function of getBusPacket(), that is, let the packet with HardPFReq keep its
original cmd: MemCmd::HardPFReq and go through the lower cache levels. The
default behavior for this is to change the cmd of the HardPFReq request
packet into ReadReq.
In my first email, the strange request whose MasterId is 13 is a ReadReq,
but its isPrefetch() is True. That's why I feel so confused. Based on my
above modification, a ReadReq should definitely not be a HardPFReq. It
should a regular demand request from CPU.
isPrefetch() is defined as:
bool isPrefetch() const { return _flags.isSet(PREFETCH); }
I search all the code but can't find where the flag "PREFETCH' is set. It's
so strange.
On the other hand,
About _dataMasterId, it is defined and used as follows:
MasterID _dataMasterId; // this is the original definition
BaseCPU::BaseCPU(Params *p, bool is_checker): ...
_dataMasterId(p->system->getMasterId(name() + ".data"))
// this is its initialization
/** Reads this CPU's unique data requestor ID */
MasterID dataMasterId() { return _dataMasterId; } // this is its wrapping
/** Read this CPU's data requestor ID */
MasterID masterId() const { return cpu->dataMasterId(); } // this is one
of its uses
Fault TimingSimpleCPU::readMem(...)
{
RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
_cpuId, tid); // this is its another typical use
}
// dataMasterId() is used to generate a read request
Thank you all the same.
gjins
On Sat, Mar 26, 2016 at 7:10 PM, Debiprasanna Sahoo <
[email protected]> wrote:
> Hi gjins,
>
> 18 Master IDs with single core system simulation? Sounds different from my
> experience. Let the Devs answer this.
>
> But if just do grep for MasterID, this is the import thing I get :
>
> src/cpu/base.hh: MasterID _instMasterId;
> src/cpu/base.hh: MasterID _dataMasterId;
>
>
>
> Regards,
> Debiprasanna Sahoo
>
> On Sat, Mar 26, 2016 at 7:00 PM, Gongjin Sun <[email protected]> wrote:
>
>> Hi Debiprasanna,
>>
>> Thank you for your answer. I simulated CPU2006 with a single X86 core
>> and SE mode. I started my simulation from a checkpoint I created before and
>> used a switch "--standard-switch".
>>
>> Why do you think MasterId is the "port number" of a cpu which issued a
>> request? Do you find any comments about this?
>>
>> I thought each MasterId represents one unique kind of request, simply, it
>> can differentiate different request types. But you mentioned the
>> terminology "port number", it looks like a physical concept. Could you
>> please explain it in more detail? I read all code related to MasterId, but
>> can't find its any relation to a "port". Also, I remember port is a
>> specific concept and is only used to connect different MemObject s, right?
>>
>> Thank you
>>
>> gjins
>>
>> On Sat, Mar 26, 2016 at 6:41 PM, Debiprasanna Sahoo <
>> [email protected]> wrote:
>>
>>> Hi gjins,
>>>
>>> MasterId is the port number from which requested from the CPU. A CPU can
>>> have a master ID for instruction (switch_cpu.inst) or data
>>> (switch_cpu.data).
>>>
>>> Writebacks(wbMasterId) are also handled by a separate MasterId. The
>>> number of master ids depends on the number of cores you are using for
>>> simulation.
>>>
>>> How many cores you are simulating? Are you using fast-forward options ?
>>>
>>> Regards,
>>> Debiprasanna Sahoo
>>>
>>> On Sat, Mar 26, 2016 at 1:08 PM, Gongjin Sun <[email protected]> wrote:
>>>
>>>> Hi All,
>>>>
>>>> The MasterId is defined in src/mem/request.hh. There are four specific
>>>> MasterIds: wbMasterId, funcMasterId, intMasterId and invldMasterId.
>>>> According to some comments, MasterID is used to generate request.
>>>>
>>>> However, during my many simulations, I printed the size of MasterId
>>>> (masterIds.size(), that is, the total of MasterIds) and found that the
>>>> total number of MasterId in system are more than 4. For example, in one of
>>>> my simulations, there are 18 MasterIds. One of them is 13, its MasterId's
>>>> name is switch_cpus.data, and its request type is ReadReq. I am curious
>>>> what kind of request is this.
>>>>
>>>> I thought most common requests we see should be covered by the above
>>>> specific ones, like funcMasterId which should cover the usual demand
>>>> read/write requests from cpu. So my confusion is why I still see so many
>>>> (up to 18) MasterIds in my simulation? Besides the four specific ones, why
>>>> do we still need other MasterIds and what are the rest uses for?
>>>>
>>>> In addition, are "all the ReadReq/WriteReq which are generated by cpu"
>>>> demand requests just from load/store instructions?
>>>>
>>>> Any help are very appreciated.
>>>>
>>>> gjins
>>>>
>>>>
>>>>
>>>> _______________________________________________
>>>> gem5-users mailing list
>>>> [email protected]
>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>>
>>>
>>>
>>> _______________________________________________
>>> gem5-users mailing list
>>> [email protected]
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>
>>
>> _______________________________________________
>> gem5-users mailing list
>> [email protected]
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>
>
> _______________________________________________
> gem5-users mailing list
> [email protected]
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
